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Instruction Set Architecture » History » Revision 16

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Alexander Kamkin, 03/17/2023 03:23 PM

Instruction Set Architecture

Section Subsection Specified instruction
Data processing - immediate Arithmetic (immediate) 12
Logical (immediate) 10
Move (wide immediate) 6
Move (immediate) 6
PC-relative address calculation 2
Extract register 2
In total: 38
Data processing - register Arithmetic (shifted register) 12
Arithmetic (extending register) 12
Logical (shifted register) 20
Move (register) 4
Multiply and divide 18
Divide 4
In total: 70
Branches, Exception generation, and System instructions Conditional branch 7
Unconditional branch (immediate) 2
Unconditional branch (register) 3
Exception generation and return 10
System register instructions 6
System instructions 8
Hint instructions 7
Barriers and CLREX instructions 4
In total: 47
Loads and stores Load/store register 2
Load-Exclusive/Store-Exclusive 12
Load-Acquire/Store-Release 20
In total: 34

Data processing - immediate

Arithmetic (immediate)

  1. ADD (immediate). Add.
    Specification: add, add_32
  2. SUB (immediate). Subtract.
    Specification: sub, sub_32
  3. ADDS (immediate). Add and set flags.
    Specification: adds, adds_32
  4. SUBS (immediate). Subtract and set flags.
    Specification: subs, subs_32
  5. CMP (immediate). Compare.
    Specification: cmp, cmp_32
  6. CMN (immediate). Compare negative.
    Specification: cmn, cmn_32

In total: 12.

Logical (immediate)

  1. AND (immediate). Bitwise AND
    Specification: and_bitmask, and_bitmask_32
  2. ANDS (immediate). Bitwise AND and set flags
    Specification: ands_bitmask, ands_bitmask_32
  3. EOR (immediate). Bitwise exclusive OR
    Specification: eor_bitmask, eor_bitmask_32
  4. ORR (immediate). Bitwise inclusive OR
    Specification: orr_bitmask, orr_bitmask_32
  5. TST (immediate). TST Test bits
    Specification: tst_bitmask, tst_bitmask_32

In total: 10.

Move (wide immediate)

  1. MOVZ. Move wide with zero
    Specification: movz, movz_32
  2. MOVN. Move wide with NOT
    Specification: movn, movn_32
  3. MOVK. Move wide with keep
    Specification: movk, movk_32

In total: 6.

Move (immediate)

  1. MOV (wide immediate). Move (wide immediate)
    Specification: mov_wide_imm, mov_wide_imm_32
  2. MOV (inverted wide immediate). Move (inverted wide immediate)
    Specification: mov_inv_wide_imm, mov_inv_wide_imm_32
  3. MOV (bitmask immediate). Move (bitmask immediate)
    Specification: mov_bitmask, mov_bitmask_32

In total: 6.

PC-relative address calculation

  1. ADRP. Compute address of 4KB page at a PC-relative offset
    Specification: adrp
  2. ADR. Compute address of label at a PC-relative offset.
    Specification: adr

In total: 2.

Extract register

  1. EXTR. Extract register from pair
    Specification: extr, extr_32

In total: 2.

Data processing - register

Arithmetic (shifted register)

  1. ADD (shifted register). Add
    Specification: add_sh_reg, add_sh_reg_32
  2. ADDS (shifted register). Add and set flags
    Specification: adds_sh_reg, adds_sh_reg_32
  3. SUB (shifted register). Subtract
    Specification: sub_sh_reg, sub_sh_reg_32
  4. SUBS (shifted register). Subtract and set flags
    Specification: subs_sh_reg, subs_sh_reg_32
  5. CMN (shifted register). Compare negative
    Specification: cmn_sh_reg, cmn_sh_reg_32
  6. CMP (shifted register). Compare
    Specification: cmp_sh_reg, cmp_sh_reg_32

In total: 12.

Arithmetic (extending register)

  1. ADD (extended register). Add
    Specification: add_ex_reg, add_ex_reg_32
  2. ADDS (extended register). Add and set flags
    Specification: adds_ex_reg, adds_ex_reg_32
  3. SUB (extended register). Subtract
    Specification: sub_ex_reg, sub_ex_reg_32
  4. SUBS (extended register). Subtract and set flags
    Specification: subs_ex_reg, subs_ex_reg_32
  5. CMN (extended register). Compare negative
    Specification: cmn_ex_reg, cmn_ex_reg_32
  6. CMP (extended register). Compare
    Specification: cmp_ex_reg, cmp_ex_reg_32

In total: 12.

Logical (shifted register)

  1. AND (shifted register). Bitwise AND
    Specification: and_bitwise, and_bitwise_32
  2. ANDS (shifted register). Bitwise AND and set flags
    Specification: ands_bitwise, ands_bitwise_32
  3. BIC (shifted register). Bitwise bit clear
    Specification: bic_bitwise, bic_bitwise_32
  4. BICS (shifted register). Bitwise bit clear and set flags
    Specification: bics_bitwise, bics_bitwise_32
  5. EON (shifted register). Bitwise exclusive OR NOT
    Specification: eon_bitwise, eon_bitwise_32
  6. EOR (shifted register). Bitwise exclusive OR
    Specification: eor_bitwise, eor_bitwise_32
  7. ORR (shifted register). Bitwise inclusive OR
    Specification: orr_bitwise, orr_bitwise_32
  8. MVN. Bitwise NOT
    Specification: mvn_bitwise, mvn_bitwise_32
  9. ORN (shifted register). Bitwise inclusive OR NOT
    Specification: orn_bitwise, orn_bitwise_32
  10. TST (shifted register). Test bits
    Specification: tst_bitwise, tst_bitwise_32

In total: 20.

Move (register)

  1. MOV (register). Move register
    Specification: mov_reg, mov_reg_32
  2. MOV (to/from SP). Move register to SP or move SP to register
    Specification: mov_sp, mov_sp_32

In total: 4.

Multiply and divide

  1. MADD. Multiply-add
    Specification: madd, madd_32
  2. MSUB. Multiply-subtract
    Specification: msub, msub_32
  3. MNEG. Multiply-negate
    Specification: mneg, mneg_32
  4. MUL. Multiply
    Specification: mul, mul_32
  5. SMADDL. Signed multiply-add long
    Specification: smaddl
  6. SMSUBL. Signed multiply-subtract long
    Specification: smsubl
  7. SMNEGL. Signed multiply-negate long
    Specification: smnegl
  8. SMULL. Signed multiply long
    Specification: smull
  9. SMULH. Signed multiply high
    Specification: smulh
  10. UMADDL. Unsigned multiply-add long
    Specification: umaddl
  11. UMSUBL. Unsigned multiply-subtract long
    Specification: umsubl
  12. UMNEGL. Unsigned multiply-negate long
    Specification: umnegl
  13. UMULL. Unsigned multiply long
    Specification: umull
  14. UMULH. Unsigned multiply high
    Specification: umulh

In total: 18.

Divide

  1. SDIV. Signed divide
    Specification: sdiv, sdiv_32
  2. UDIV. Unsigned divide
    Specification: udiv, udiv_32

In total: 4.

Branches, Exception generation, and System instructions

Conditional Branch

  1. B.cond. Branch conditionally
    Specification: b
  2. CBNZ. Compare and branch if nonzero
    Specification: cbnz, cbnz_32
  3. CBZ. Compare and branch if zero
    Specification: cbz, cbz_32
  4. TBNZ. Test bit and branch if nonzero
    Specification: tbnz
  5. TBZ. Test bit and branch if zero
    Specification: tbz

In total: 7.

Unconditional branch (immediate)

  1. B. Branch unconditionally
    Specification: b_imm
  2. BL. Branch with link
    Specification: bl

In total: 2.

Unconditional branch (register)

  1. BLR. Branch with link to register
    Specification: blr
  2. BR. Branch to register
    Specification: br
  3. RET. Return from subroutine
    Specification: ret

In total: 3.

Exception generation and return

Exception generation

  1. BRK. Breakpoint Instruction
    Specification: brk
  2. HLT. Halt Instruction HLT
    Specification: hlt
  3. HVC. Generate exception targeting Exception level 2 HVC
    Specification: hvc
  4. SMC. Generate exception targeting Exception level 3 SMC
    Specification: smc
  5. SVC. Generate exception targeting Exception level 1
    Specification: svc

In total: 5.

Exception return

  1. ERET. Exception return using current ELR and SPSR
    Specification: eret

In total: 1.

Debug state

  1. DCPS1. Debug switch to Exception level 1 DCPS1
    Specification: dcps1
  2. DCPS2. Debug switch to Exception level 2 DCPS2
    Specification: dcps2
  3. DCPS3. Debug switch to Exception level 3 DCPS3
    Specification: dcps3
  4. DRPS. Debug restore PE state
    Specification: drps

In total: 4.

System register instructions

  1. MRS. Move System register to general-purpose register MRS
    Specification: msr
  2. MSR. Move general-purpose register to System register MSR (register)
    Specification: mrs
  3. MSR. Move immediate to PE state field MSR (immediate)
    Specification: msr_dc, msr_ds, msr_ss, msr_uao

In total: 6.

System instructions

  1. SYS. System instruction
    Specification: sys
  2. SYSL. System instruction with result
    Specification: sysl
  3. IC. Instruction cache maintenance
    Specification: ic, ic_reg
  4. DC. Data cache maintenance
    Specification: dc
  5. AT. Address translation
    Specification: at
  6. TLBI. TLB Invalidate
    Specification: tlbi, tlbi_reg

In total: 8.

Hint instructions

  1. NOP. No operation
    Specification: nop
  2. YIELD. Yield hint
    Specification: yield_op
  3. WFE. Wait for event
    Specification: wfe
  4. WFI. Wait for interrupt
    Specification: wfi
  5. SEV. Send event
    Specification: sev
  6. SEVL. Send event local
    Specification: sevl
  7. HINT. Unallocated hint
    Specification: hint

In total: 7.

Barriers and CLREX instructions

  1. CLREX. Clear Exclusives monitor
    Specification: clrex
  2. DMB. Data memory barrier
    Specification: dmb
  3. DSB. Data synchronization barrier
    Specification: dsb
  4. ISB. Instruction synchronization barrier
    Specification: isb

In total: 4.

Loads and stores

Load/store register

  1. LDR. Load register (immediate offset)
    Specification: ldr_postindex
  2. STR. Store register (immediate offset)
    Specification: str_postindex

In total: 2.

Load-Exclusive/Store-Exclusive

  1. LDXR. Load Exclusive register
    Specification: ldxr, ldxr_32
  2. LDXRB. Load Exclusive byte
    Specification: ldxrb_32
  3. LDXRH. Load Exclusive halfword
    Specification: ldxrh_32
  4. LDXP. Load Exclusive pair
    Specification: ldxp, ldxp_32
  5. STXR. Store Exclusive register
    Specification: stxr, stxr_32
  6. STXRB. Store Exclusive byte
    Specification: stxrb_32
  7. STXRH. Store Exclusive halfword
    Specification: stxrh_32
  8. STXP. Store Exclusive pair
    Specification: stxp, stxp_32

In total: 12.

Load-Acquire/Store-Release

Non-exclusive Load-Acquire and Store-Release instructions

  1. LDAR. Load-Acquire Register
    Specification: ldar, ldar_32
  2. LDARB. Load-Acquire Byte
    Specification: ldarb
  3. LDARH. Load-Acquire Halfword
    Specification: ldarh
  4. STLR. Store-Release Register
    Specification: stlr, stlr_32
  5. STLRB. Store-Release Byte
    Specification: stlrb
  6. STLRH. Store-Release Halfword
    Specification: stlrh

In total: 8.

Exclusive Load-Acquire and Store-Release instructions

  1. LDAXR. Load-Acquire Exclusive register
    Specification: ldaxr, ldaxr_32
  2. LDAXRB. Load-Acquire Exclusive byte
    Specification: ldaxrb_32
  3. LDAXRH. Load-Acquire Exclusive halfword
    Specification: ldaxrh_32
  4. LDAXP. Load-Acquire Exclusive pair
    Specification: ldaxp, ldaxp_32
  5. STLXR. Store-Release Exclusive register
    Specification: stlxr, stlxr_32
  6. STLXRB. Store-Release Exclusive byte
    Specification: stlxrb_32
  7. STLXRH. Store-Release Exclusive halfword
    Specification: stlxrh_32
  8. STLXP. Store-Release Exclusive pair
    Specification: stlxp, stlxp_32

In total: 12.

Pseudo instructions

psldr, psldr32

In total: 2.

Updated by Alexander Kamkin almost 2 years ago · 17 revisions