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Using C++TESK and SystemVerilog together

SystemVerilog is a HDL-language developed for creation CRV-testbenches, coverages, and so on, with many proven approaches based upon it.

In case of merging a test system created by means of C++TESK and some components based on SystemVerilog,
the following tasks can be solved by some or other element of merged test system:

1) creating of stimuli flow by means of C++TESK FSM traversers
2) developing reference model showing correct results by means of SystemVerilog
3) checking the implementation reactions be means of C++TESK Test Oracle
4) checking functional coverage by means of C++TESK
5) checking event sequence coverage by means of SystemVerilog

How to connect C++TESK and SystemVerilog parts is shown in counter_sv example included into C++TESK distribution package.

Here we are going to only mention the most important modifications of original test systems (in case of Synopsys' VCS simulator):

1) Files with reference model and test coverage written on SystemVerilog should be created (see counter.sv and coverages.sv);
2) C-functions for DPI connection should be created near to the C++TESK test system model (see counter_model.h and counter_model.cpp);
3) A file with additional setting for DPI-connection should be added (see dut.tab);
4) Set of Makefiles may be simply copied to the new test system;
5) Files testbench.v, vpi_systf.h, and vpi_systf.cpp should be modified as it is shown in the example: system tasks should be declared as extern "C", the reference model written in SystemVerilog should be instantiated in testbench.v.

Updated by Mikhail Chupilko over 10 years ago ยท 2 revisions