C++TESK Testing ToolKit

h1. FAQ

* *Where is it possible to get C++TESK Testing ToolKit?*

The toolkit is located at the following link: http://forge.ispras.ru/projects/cpptesk-toolkit/files.

* *What are the steps to have the toolkit correctly installed?*

1. Download and unpack the archive with C++TESK Testing ToolKit (the lastest version) into a convenient folder;

2. Run install.sh from the folder with C++TESK Testing ToolKit;

3. Wait until "Successfully installed" appears.

The toolkit is installed into $(CPPTESK_HOME) folder. If this environment variable is missing, it will be assigned to $(ISPRAS_HOME)/tools/cpptesk-toolkit. If the varible $(ISPRAS_HOME) is missing, this varible first will be assigned to $HOME.

* *What other programs should be installed for verification of hardware designs?*

There are Icarus Verilog and VeriTool being able to be installed by means of $(CPPTESK_HOME)/bin/install-veritool.sh.

Icarus Verilog is installed into $(ICARUS_HOME), and VeriTool is installed into $(VERITOOL_HOME). If the variables are missing, they will be created like $(CPPTESK_HOME).

* *Is it possible to reduce size of the signal dump file (VCD)?*

E.g. in Icarus Verilog it is possible to choose different dump file format LXT2. The running command would be as follows: $(ICARUS_HOME)/bin/vvp -M. -mdb $(DB_VVP) -lxt2 -M. +scen=$@ +argv="$(TEST_ARGV)". To use GTKWave for viewing the file is possible if testbench.vcd is renamed to testbench.lxt.

* *What does the following message mean*

<pre>

 tests/src/scenarios/fifo_scen.cpp: In member function ''bool cpptesk::examples::fifo::FIFOScenario::scen_nop(cpptesk::ts::IntAbcCtx&)'':

 tests/src/scenarios/fifo_scen.cpp:62: error: jump to case label

 tests/src/scenarios/fifo_scen.cpp:55: error:   crosses initialization of ''int i''

</pre>

 *during compiling of the following code?*

<pre>

 50:bool FIFOScenario::scen_nop(Ctx& ctx)

 51:{

 52:    IBEGIN

 53:    IACTION

 54:    {

 55:        int i = 0;

 56:        // Refresh functional coverage

 57:        dut.refresh_coverage();

 58:        // Give control to the simulator for one cycle

 59:        dut.cycle();

 60:

 61:        // Take results of reference model working and check them

 62:        YIELD(dut.verdict());

 63:    }

 64:    IEND

 65:}

</pre>

There is an agreement not to declare local variables inside of IACTION first block. If a nested into IACTION block is used, the problem will disappear. Also it is possible to declare variables before IBEGIN.

* *Is it necessary to place CYCLE () after WAIT (condition)?*

No, it is not. The macro WAIT (condition) includes CYCLE () itself. The semantics of the CYCLE after the WAIT is as follows. We ask the interface adapter to wait one cycle more after the WAIT''s condition is met.

* *How to call a serializer?*

It can be called by means of one of the following macro:

START_STIMULUS(SEQUENTIAL|PARALLEL)

RECV_STIMULUS(SEQUENTIAL|PARALLEL, Interface iface, Message msg)

* *What is the difference between START_STIMULUS and RECV_STIMULUS?*

START_STIMULUS starts serializer with default parameters (interface and message are the same as those given to the stimuli process). RECV_STIMULUS allows modifing both message and name of the interface used. The macro is also useful if there is a stimulus with more than one serializer call inside.