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Verilog Translator 0.1.3 released

Verilog Translator 0.1.3 has been released
Added by Sergey Smolov 24 days ago

The release includes the following changes:

  • Build system: use Gradle 5.0;
  • Documentation: changelog and readme are rewritten into Markdown format;
  • Language: support for macro with parameters;
  • Language: support for SystemVerilog Assertions;
  • Options: `--library-file` option to include function library files;
  • Tests: test cases for QUIP and IWLS'2005 benchmarks;
  • Tool: bug fixes and general improvements;
  • Tool: error diagnostics is improved;
  • Tool: migration to Java 11.

The tool can be downloaded from here
The list of resolved issues can be found here


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