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Verilog Translator 0.1.2 released

Verilog Translator 0.1.2 has been released.
Added by Sergey Smolov 2 months ago

The release includes the following changes:
  • Type casting for case statement's expression and values;
  • Fix 'publishing' block behaviour in Gradle build system;
  • Bug fixes and general improvements.

The list of resolved issues can be found here

The tool can be downloaded from here


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