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Verilog Translator 0.1.1 released.

We are happy to announce the first release of the Verilog Translator tool.
Added by Sergey Smolov 3 months ago

Verilog Translator (VeriTrans) is an ANTLR-based Verilog front-end that generates an internal
representation of the target description. The representation is based on an Abstract Syntax Tree
(AST) formalism and on Fortress library objects for expressions representation.

The tool can be downloaded from here


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