Retrascope

The new release contains the following changes:

• CGAA model: phase variable based representation;
• CGAA model: process as a collection of sub-paths;
• CGAA-to-EFSM transformer: cmdline parameter for EFSM state number limit;
• EFSM model: phase variable based representation;
• HLDD model: phase variable based representation support;
• HLDD-based test generator: phase variable based representation support;
• Tests: miniMIPS & Plasma projects are partially in use;
• Tool Functions: Bug fixes & general improvements;
• Utilities: separately solve independent sub-expressions of AND expression;
• VHDL parser: flatten module instances;
• VHDL parser: enum support;
• VHDL parser: support for 'others' attr upon bitvector\array initialization;
• VHDL parser: limited support for functions (BV_INC6);
• VHDL\Verilog parsers: backend that merges "neighbour ranged" sequential "if" statements;
• VHDL\Verilog parsers: backend that merges empty event-free cases.

The list of resolved issues can be found here

The tool can be downloaded from here