HDL Retrascope v0.1.2 released
HDL Retrascope v0.1.2 has been released.
The new release includes the following changes:
- Support for loops in VHDL/Verilog designs;
- Support for wait-expressions in VHDL/Verilog designs;
- Support for hierarchical (i.e. having sub-modules) VHDL/Verilog designs;
- Support for concurrent (non-blocking) statements in VHDL/Verilog designs;
- New command line scripts for Windows & Unix;
- New heuristic for initial EFSM state & reset signal detection;
- New fully-functional *.tar.gz distribution format;
- A number of bugs was fixed.
The tool can be downloaded from here: http://forge.ispras.ru/projects/retrascope/files