HDL Retrascope v0.1.1 released
HDL Retrascope v0.1.1 has been released
We are happy to announce the first build of the HDL Retrascope toolkit.
HDL Retrascope is a toolkit for Reverse Engineering and TRAnsformation of digital hardware designs described in such HDLs (hardware description languages) as Verilog и VHDL. The toolkit allows analyzing HDL descriptions, reconstructing the underlying models (extended finite state machines, EFSMs) and using the derived models for test generation, property checking and other tasks. HDL Retrascope is organized as an extendable framework with the ability to add new types of models as well as tools for their analysis and transformation. The primary application domain of the toolkit is functional verification of hardware at the unit level.
To reconstruct EFSM models and generate tests for them, Retrascope requires the SMT-solver be installed. See Installation Guide for more information.
In the 0.1.1 build the following features have been implemented:
- Support for VHDL/Verilog little-size designs (without iteration loops/functions/sub-modules);
- Support for control flow graph (CFG) construction;
- Support for CFG visualization in GraphML format;
- Support for interface signals extraction from CFG;
- Support for guarded actions decision diagram (GADD) construction;
- Support for GADD visualization in GraphML format;
- Support for extended finite state machine (EFSM) extraction;
- Support for EFSM visualization in GraphML format;
- Support for read/write conflicts extraction from EFSM;
- Support for conflicts saving into XML format;
- Support for test sequences generation for EFSM;
- Support for test sequences saving into VHDL testbenches/XML format.
The tool can be downloaded from here: http://forge.ispras.ru/projects/retrascope/files
You are welcome to report bugs and leave your feedback at the main project site: http://forge.ispras.ru/projects/retrascope
Merry Christmas and Happy New Year!