MicroTESK for RISC-V: MicroTESK for RISC-V 0.0.9 released

Added by Alexander Kamkin about 2 months ago

What's new?

  • Specifications: Added system registers and the related modes
  • Specifications: Added sample specifications of some vector instructions (consistent with RISC-V "V" Vector Extension Version 0.7.1)
  • Specifications: Fixed bugs in RV64A instructions
  • Specifications: Fixed bugs in RV32{F,D} instructions (FEQ, FLE, and FLT)
  • Test Templates: Added sample test templates for vector instructions
  • Test Templates: Changed structure of directories
  • Test Templates: Fixed a Torture-like template (synthetics/rvxxx)
  • Tool Functions: Moved branch data generators to TestBase
  • Tests: Test suite uses QEMU4V 0.3.3


Local Support Project: Redmine 4.0.5

Added by Alexey Demakov about 2 months ago

Уважаемые коллеги!

Redmine обновился до версии 4.0.5.

Jenkins обновился до версии 2.190.1

Debian обновился до версии 10.1

Просьба сообщать об обнаруженных проблемах.

Retrascope: Retrascope 1.1.2 released

Added by Sergey Smolov 3 months ago

The new release includes the following changes:

  • CFG-to-GraphML printer: mark branch values with italic;
  • CFG-to-GraphML printer: use dotted arrows for hierarchy dependencies;
  • Dependencies: does not use commons-lang library;
  • Tool: bug fixes and general improvements.

The list of resolved issues is available here

The tool can be downloaded from here

Verilog Translator: Verilog Translator 0.1.2 released

Added by Sergey Smolov 3 months ago

The release includes the following changes:
  • Type casting for case statement's expression and values;
  • Fix 'publishing' block behaviour in Gradle build system;
  • Bug fixes and general improvements.

The list of resolved issues can be found here

The tool can be downloaded from here

Retrascope: Retrascope 1.1.1 released

Added by Sergey Smolov 5 months ago

The new release includes the following changes:
  • Assertion: renamed to Property;
  • CFG Model: CFG model processes do not have their own internal variables: variable space is flattened at parent module's level;
  • CFG-to-GADD transformer: backend that implements clock detection is moved here;
  • CFG-to-GADD transformer: cmdline option that specifies clock variable;
  • CFG-to-GADD transformer: elaborate ranged assignments for bit vector target variables;
  • CFG-to-GADD transformer: one more auxiliary path in GADD model for terminal endings;
  • CFG-to-GADD transformer: reuse variables' versions upon CGAA model building;
  • CFG-to-GADD transformer: support for designs that assign to variable more than once;
  • CGAA model: renamed to GADD;
  • Engines: '--no-backends' cmdline option;
  • Engines: new cgaa-assert-extractor engine that extracts 'is-def' and 'is-use' constraints for every variable of every process of the design;
  • Engines: debug output file for engines and their back-ends;
  • Engines: enable\disable backend option by name for all engines;
  • HDL Parser: init_process backend that transforms initial blocks;
  • Models: support for 'BVEXTRACT(x y (SELECT z w))' constructions in left hand sides of assignments;
  • Model Checker Launcher: nuXmv 1.1.1 is in use;
  • Model Checker Launcher: pass Retrascope debug option to the model checker as well;
  • Model Checker Launcher: pass model checker error msg to the Retrascope output;
  • Refactoring: Range class is moved to Castle library;
  • Refactoring: RetrascopeException.makeException -> RetrascopeException.exception;
  • Refactoring: use StringTemplate facilities to generate HDL testbenches;
  • SAT Solver wrapper: z3 4.7.1 is in use;
  • Test suite: check variables\switches\basic blocks number at HDL parser test cases;
  • Test suite: jUnit test cases for CFG-GADD transformer that check path number;
  • Test suite: separate jUnit test cases for EfsmGraphMlPrinter engine;
  • Tool: bug fixes and general improvements;
  • Tool: renamed from "HDL Retrascope" to "Retrascope";
  • Utility: 'BVEXTRACT( ... BVEXTRACT (j i x))' expression transformation rule to the tool ruleset;
  • Utility: check BVEXTRACT operation's parameter order;
  • Utility: substitute SMT-LIB variables those names are equal to builtin commands;
  • VHDL parser: VHDL record support (non-aggregate case);
  • VHDL parser: ZamiaCAD 0.11.3 is in use.

The list of resolved issues can be found here

The tool can be downloaded from here


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