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# Project Tracker Status Priority Subject Author Assignee Target version
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9784 Verilog Translator Bug Resolved Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9776 Retrascope IDE Task New Normal try to use SVEditor instead of veditor Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9775 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9771 Verilog Translator Task Resolved Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9769 Retrascope Feature Resolved Normal GraphML printers: make branch values italic Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9767 Retrascope Feature Resolved Normal GraphML printers: use dotted arrows for Module->(Module| Process) hierarchy dependencies Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9766 Retrascope Task Closed High remove 'vhdl.record' Git branch from remote repo Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
9764 Retrascope IDE Task New Normal migrate to Eclipse 2019 Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9763 Retrascope MC Benchmark Bug Closed Normal missing javadoc headers in Java files of 'ru.ispras.retrascope.engine.hldd.printer.smv.spec.sample.vcegar' package Sergey Smolov Mikhail Lebedev Actions
9762 Retrascope Task Closed High prepare to 1.1.1 release Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9726 Retrascope MC Benchmark Task Closed Normal VerilogPrinter test cases Sergey Smolov Sergey Smolov Actions
9670 Retrascope MC Benchmark Task New Normal add 'ar.v' module to the test suite when SVA support will be implemented Sergey Smolov Sergey Smolov Actions
9658 Retrascope Task Closed Normal Check for duplicated data access conflict assertions Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9607 Retrascope MC Benchmark Task Closed Normal add QUIP 9.0 benchmark Sergey Smolov Sergey Smolov Actions
9606 Retrascope MC Benchmark Task Closed Normal add IWLS 2005 benchmark Sergey Smolov Sergey Smolov Actions
9594 Verilog Translator Bug Open Normal extra 'BVEXTRACT' operation in right hand side expression in 'assign' block's statement Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9566 Retrascope MC Benchmark Task Closed Normal tests for Yosys-SMTBMC tool Sergey Smolov Sergey Smolov Actions
9565 Retrascope MC Benchmark Task Closed Normal tests for Verilog2SMV tool Sergey Smolov Sergey Smolov Actions
9564 Retrascope MC Benchmark Task Closed Normal tests for EBMC tool Sergey Smolov Sergey Smolov Actions
9562 Retrascope Bug Closed Normal ru.ispras.retrascope.engine.hldd.printer.smv.usedef.MemStageUseDefSmvPrinterTestCase: model checker crashes without errors in *.smvlog Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9521 Retrascope Bug Closed High NuSMV works too slow on ITC'99 b11 design Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9503 Retrascope Feature Closed Normal when debug option is enabled, pass it to the model checker as well Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9488 Retrascope Task New Normal CFG-GADD transformer backend that makes assignments index and range-free Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
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