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# Project Tracker Status Priority Subject Author Assignee Target version
10513 Verilog Translator Bug New Normal macOS related line endings at Verilog modules Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10512 Verilog Translator Bug New Normal ADDA162H90A_atop.v line 120:47 mismatched input ':' expecting RPAREN Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10510 Verilog Translator Bug New Normal ERROR: [Internal] Bit vector sizes do not match: 32 != 2. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10509 Verilog Translator Bug New Normal ERROR: [Internal] 0 must be > 0 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10508 Verilog Translator Bug New Normal ERROR: [Internal] Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10505 Verilog Translator Bug New Normal ERROR: [Internal] 11 must be within range [0, 1) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10502 Verilog Translator Bug New Normal subbytes.v line 76:13 no viable alternative at input '[' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10382 Verilog Translator Bug Closed Normal java.lang.IllegalArgumentException: expression=(BVREPEAT test.uut._saxi_maskwidth 1) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10370 Fortress Bug Closed Normal class ru.ispras.fortress.solver.constraint.Formulas cannot be cast to class ru.ispras.fortress.solver.constraint.Sat4jFormula Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
10289 Retrascope Bug Verified Normal ru.ispras.retrascope.engine.hldd.printer.smv.property.HlddPropertySmvPrinterTestCase.runTest: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Mikhail Lebedev Retrascope - 1.1 Actions
10266 Retrascope Bug Verified Normal ru.ispras.retrascope.engine.hldd.printer.smv.HlddSmvPrinterTestCase.runTest: java.lang.NullPointerException Sergey Smolov Mikhail Lebedev Retrascope - 1.1 Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10245 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_pci_wbw_wbr_fifos: ERROR: [Internal] null Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10241 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_dctub_jpeg: ERROR: ..\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 1:70 mismatched character '\r' expecting '\n' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10237 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10236 Retrascope Bug Rejected Normal efsm-test-generator hangs at opencores/mips16/data_mem.v Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10216 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10215 Verilog Translator Bug New Normal ERROR: Starting points limit has been exhausted: 2255 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10202 Verilog Translator Bug Closed Normal SVA grammar warnings via assembling Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
10191 Retrascope Bug Resolved Normal java.lang.IllegalArgumentException: Specified target vertex 0 is not part of graph Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10174 Retrascope Bug Verified High nondeterminism at EFSM transitions generation Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10173 Verilog Translator Bug Closed High javadoc: DefineStructure.java:37: warning: no @return Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10141 Verilog Translator Bug Closed Normal check port redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10131 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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