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# Project Tracker Status Priority Subject Author Assignee Target version
9184 Veritool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
9478 Retrascope RISC-V Benchmark Bug New Normal ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int' Sergey Smolov Actions
9012 Retrascope Test Suite Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
4004 C++TESK Testing ToolKit Bug Closed Normal Из build'а пропал скрипт install-eclipse-plugin.sh Sergey Smolov Sergey Smolov C++TESK Testing ToolKit - 1.0 Actions
3590 C++TESK Testing ToolKit Bug Closed Normal C++TesK installation fails on OpenSUSE 12.2 x64 Sergey Smolov Sergey Smolov C++TESK Testing ToolKit - 1.0 Actions
9437 MicroTESK Bug Closed Normal ru.ispras.microtesk.model.minimips.BufferPreparatorTestCase: QEMU4V crashes with general protection error on this test program Sergey Smolov Sergey Smolov MicroTESK - 2.4 Actions
10382 Verilog Translator Bug Closed Normal java.lang.IllegalArgumentException: expression=(BVREPEAT test.uut._saxi_maskwidth 1) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9822 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7098 Verilog Translator Bug Closed Normal src/test/verilog/mips16/data_mem.v: 'mem_access_addr' has null declaration Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8786 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.FifoTestbenchTestCase fails Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7474 Verilog Translator Bug Closed Normal missing empty branches for 'if' statements Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9848 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9784 Verilog Translator Bug Closed Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9209 Verilog Translator Bug Closed High java.util.EmptyStackException at ru.ispras.verilog.parser.util.TokenSourceStack.getLastParentToken(TokenSourceStack.java:70) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
4836 Retrascope Bug Closed Normal [cfg][transformer][cgaa] java heap space error at control.vhd\mlite2sram.vhd Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4926 Retrascope Bug Closed Normal [cfg][model] Путаница с наследниками CfgNode Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4357 Retrascope Bug Closed Normal [cfg][transformer][cgaa] Внести исправления в методы извлечения clock-like variables Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6413 Retrascope Bug Closed Normal b03.vhd: different EFSM extraction stats Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5873 Retrascope Bug Closed High missing transitions in b04 EFSM Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4928 Retrascope Bug Rejected Normal [cfg] Range может состоять из нескольких участков Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6353 Retrascope Bug Closed Normal Case children of one Switch node can have equal NodeValue Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6281 Retrascope Bug Closed Normal EfsmTestGeneratorVhdlTestCase: Efsm.UNINITIALISED_STATE isn't supported yet Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
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