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# Project Tracker Status Priority Subject Author Assignee Target version
5648 Retrascope Bug Rejected High EfsmSimulator.executeAssignment -> Unsupported data type of ranged variable: (MAP LOGIC_INTEGER LOGIC_INTEGER) Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
7423 Retrascope Bug Rejected High rnd_fsm.vhd: empty tst file Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5263 Retrascope Bug Rejected High [efsm][generator][test] EfsmTestGeneratorTestCase -> java.lang.OutOfMemoryError: Java heap space Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
6808 Retrascope Task Rejected High Split CFG processes into independent parts Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
10236 Retrascope Bug Rejected Normal efsm-test-generator hangs at opencores/mips16/data_mem.v Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5003 Retrascope Bug Rejected Normal [util] XmlUtilTest.java: java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
3605 Retrascope Bug Rejected Normal [vhdl][parser][cfg] Zamia не обрабатывает пакеты функций Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6366 Retrascope Bug Rejected Normal src/test/vhdl/example/test.vhd: Efsm.UNINITIALISED_STATE isn't supported yet Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
5004 Retrascope Bug Rejected Normal [efsm][simulator][execution] ReferenceEfsmTestGeneratorTest.java : java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5692 Retrascope Bug Rejected Normal FATE/FATE+ hangs on b03 with Java 1.8 Sergey Smolov Igor Melnichenko Actions
4928 Retrascope Bug Rejected Normal [cfg] Range может состоять из нескольких участков Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9844 Retrascope Test Suite Bug Rejected Normal Bash scripts that run side tools (EBMC, SymbiYosys, Verilog2SMV) can't extract names of several Verilog modules Sergey Smolov Sergey Smolov Actions
7594 Retrascope Bug Rejected Normal ModelSim shows error when TST file contains multiple comments Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6362 Retrascope Bug Rejected Normal src/test/verilog/adder/adder4_testbench.v: wrong CFG model Sergey Smolov Mikhail Chupilko Retrascope - 0.1 Actions
4005 C++TESK Testing ToolKit Bug Rejected Normal удалить пустой README Sergey Smolov asd ert C++TESK Testing ToolKit - 1.0 Actions
8304 Retrascope Feature Rejected Normal SLR values number limit Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
4359 Retrascope Task Rejected Normal [cfg] Реализовать метод toConstraint() Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
7723 Retrascope Task Rejected Normal Support for module instances in Verilog descriptions Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
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