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# Project Tracker Status Priority Subject Author Assignee Target version
3756 С++TESK Development Environment Task New Immediate Генерация C++ кода для модели сообщений Sergey Smolov Actions
9993 Verilog Translator Bug New High if two modules are passed to the tool and one includes another, the tool hangs Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
4713 Fortress Task New High SMT-LIB structures Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
9670 Retrascope Test Suite Task New High add 'ar.v' module to the test suite when SVA support will be implemented Sergey Smolov Sergey Smolov Actions
9764 Retrascope IDE Task New High migrate to Eclipse 2019 Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
6394 Local Support Project Bug New Normal Проект HDL Retrascope: на 17-дюймовом мониторе не масштабируется таблица Задачи Sergey Smolov Alexey Demakov Actions
10241 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_dctub_jpeg: ERROR: ..\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 1:70 mismatched character '\r' expecting '\n' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10131 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10069 MicroTESK Bug New Normal cpu.nml Error: Internal error: context [/Isa] 1:8 attribute file isn't defined Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
9477 Retrascope RISC-V Benchmark Bug New Normal an "import "DPI-C" function" construction causes Verilog Translator error Sergey Smolov Alexander Kamkin Actions
10215 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000_lut: ERROR: Starting points limit has been exhausted: 2255 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9184 VeriTool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
10031 MicroTESK for PowerPC Bug New Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for PowerPC - 0.0 Actions
5547 Retrascope IDE Bug New Normal save Retrascope result not to ECLIPSE_HOME folder Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9377 MicroTESK for MIPS Bug New Normal 'Failed to construct decoder' warnings in project's build log Sergey Smolov Alexander Kamkin Actions
9478 Retrascope RISC-V Benchmark Bug New Normal ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int' Sergey Smolov Actions
9816 Retrascope IDE Bug New Normal Retrascope IDE does not appear in "Installed Software" menu Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9376 MicroTESK for MIPS Bug New Normal Warning: Group MIPS64FpuOp contains two items add_fmt and mfc1 with the same opcode 01000100000000000000000000000000 Sergey Smolov Alexander Kamkin Actions
10082 Retrascope Bug New Normal WARNING: Illegal reflective access by org.python.core.PySystemState Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
2494 CTESK Bug New Normal warning at build log Sergey Smolov Alexey Demakov Actions
10074 MicroTESK Feature New Normal option that stores boot obj at the generated ld script Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
8587 MicroTESK Feature New Normal ISA subsets Sergey Smolov Artem Kotsynyak MicroTESK - 2.5 Actions
10290 Verilog Translator Feature New Normal SystemVerilog support Sergey Smolov Actions
5504 Retrascope Task New Normal add channels between EFSMs Sergey Smolov Mikhail Lebedev Retrascope - 1.2 Actions
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