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# Project Tracker Status Priority Subject Author Assignee Target version
3756 С++TESK Development Environment Task New Immediate Генерация C++ кода для модели сообщений Sergey Smolov Actions
9288 QEMU4V Bug Closed Immediate /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’ Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
9911 Retrascope Task Verified Urgent merge "*/sample/*TestCase" Java test cases Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
6367 Retrascope Task Closed Urgent Fortress expressions printing in an SMV format Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
9915 Verilog Translator Bug Verified Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
5680 Retrascope Bug Closed Urgent [efsm][generator][test][fate] DirectedFateGenerator.generateSequence -> NullPointerException Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5719 Retrascope Bug Closed Urgent EFSM Test Generator hangs on b11 Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9670 Retrascope Test Suite Task New High add 'ar.v' module to the test suite when SVA support will be implemented Sergey Smolov Sergey Smolov Actions
9764 Retrascope IDE Task New High migrate to Eclipse 2019 Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
4713 Fortress Task New High SMT-LIB structures Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
10073 Retrascope Task Verified High fix checkstyle warnings Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
10139 Retrascope Task Verified High fix coding issues at *BenchTest classes Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
9811 Verilog Translator Task Verified High macro with parameters Sergey Smolov Alexey Danilov Verilog Translator - 0.2 Actions
3957 Retrascope Task Closed High DFG to EFSM Sergey Smolov Sergey Smolov Actions
5689 Retrascope Task Closed High implement test-to-Verilog printer Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6282 Retrascope Task Closed High finish AstSmvVisitor & CfgAstVisitor merge Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
9766 Retrascope Task Closed High remove 'vhdl.record' Git branch from remote repo Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
5249 Retrascope Task Closed High [basis] Настройка Retrascope для работы с SMT-решателями Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
5394 Retrascope Task Closed High [cgaa][transformer][efsm] реализовать построение переходов EFSM Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6456 Retrascope Task Closed High CFG model as hirerarchical list of statements Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9762 Retrascope Task Closed High prepare to 1.1.1 release Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
5413 Retrascope Task Closed High [model][basis] add HdlType field to VariableData class Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9277 Retrascope Task Closed High mv clock-like variable detection to CFG-to-CGAA transformer Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9242 Retrascope Task Closed High check BVEXTRACT operation's parameter order Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9248 Retrascope Task Closed High CFG model process should not have it's own internal variables Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
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