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# Project Tracker Status Priority Subject Author Assignee Target version
9288 QEMU4V Bug Closed Immediate /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’ Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
3756 С++TESK Development Environment Task New Immediate Генерация C++ кода для модели сообщений Sergey Smolov Actions
9915 Verilog Translator Bug Closed Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9911 Retrascope Task Verified Urgent merge "*/sample/*TestCase" Java test cases Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
6367 Retrascope Task Closed Urgent Fortress expressions printing in an SMV format Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
5719 Retrascope Bug Closed Urgent EFSM Test Generator hangs on b11 Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5680 Retrascope Bug Closed Urgent [efsm][generator][test][fate] DirectedFateGenerator.generateSequence -> NullPointerException Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
10237 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10216 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10174 Retrascope Bug Verified High nondeterminism at EFSM transitions generation Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10173 Verilog Translator Bug Closed High javadoc: DefineStructure.java:37: warning: no @return Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10139 Retrascope Task Verified High fix coding issues at *BenchTest classes Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
10102 MicroTESK Bug Verified High incorrect ld scripts for x86 test programs Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
10081 Retrascope Bug Resolved High tool hangs right after final "Duration: " msg Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10073 Retrascope Task Verified High fix checkstyle warnings Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
10060 Retrascope Feature Resolved High Support SVA properties in CFG model Sergey Smolov Sergey Smolov Retrascope - 1.2 Actions
10023 Retrascope Bug Verified High ru.ispras.retrascope.parser.verilog.VerilogParserTestCase: java.lang.Exception: Method runTest should have no parameters Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
9993 Verilog Translator Bug New High if two modules are passed to the tool and one includes another, the tool hangs Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9990 Verilog Translator Feature Closed High check for variable/net redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9962 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Closed High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for '<var name>' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9811 Verilog Translator Task Closed High macro with parameters Sergey Smolov Alexey Danilov Verilog Translator - 0.2 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9766 Retrascope Task Closed High remove 'vhdl.record' Git branch from remote repo Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
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