Project

General

Profile

Issues

Filters

Apply Clear

# Project Tracker Status Priority Subject Author Assignee Target version
10041 QEMU4V Bug Closed Normal wrong names for PowerPC registers in trace Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
10031 MicroTESK for PowerPC Bug New Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for PowerPC - 0.0 Actions
10023 Retrascope Bug Resolved High ru.ispras.retrascope.parser.verilog.VerilogParserTestCase: java.lang.Exception: Method runTest should have no parameters Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
10018 Trace Matcher Task Closed Normal migrate to Python 3 Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10017 Trace Matcher Task Closed Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10016 Trace Matcher Task Closed Normal Use Gradle 4.10.3 in build system Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10015 Trace Matcher Feature Closed Normal Report an error when input file is empty Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10009 Verilog Translator Task Verified Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10002 Fortress Task New Normal get Boolector solver from server as dependency Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
10001 Fortress Task New Normal SMT-LIBv2 benchmarks Sergey Smolov Actions
10000 Retrascope Task Verified Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9999 Castle Task Resolved Normal ChangeLog -> ChangeLog.md Sergey Smolov Sergey Smolov Castle - 0.1 Actions
9998 Castle Task Resolved Normal README -> README.md Sergey Smolov Sergey Smolov Castle - 0.1 Actions
9993 Verilog Translator Bug New High if two modules are passed to the tool and one includes another, the tool hangs Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9990 Verilog Translator Feature New Normal check for variable/net redeclarations Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9986 QEMU4V Task New Normal check if QEMU4V features can be implemented as TCG plugin Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
9971 MicroTESK for RISC-V Task Closed Normal print Spike trace to separate log file for every JUnit test case Sergey Smolov Sergey Smolov MicroTESK for RISC-V - 0.1 Actions
9964 Retrascope Task New Normal add examples to project distribution Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9962 Verilog Translator Bug Verified High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9961 Verilog Translator Task New Normal uncomment jUnit test cases that are related to SVA modules Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Verified High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9917 QEMU4V Task Closed Normal check QEMU4V-specific code on compliance with coding style Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
9915 Verilog Translator Bug Verified Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9911 Retrascope Task New Normal merge "*/sample/*TestCase" Java test cases Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
9909 QEMU4V Task Closed Normal migrate to QEMU 4.2.0 Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
(1-25/631) Per page: 25, 50, 100

Also available in: Atom CSV PDF