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# Project Tracker Status Priority Subject Author Assignee Target version
9184 VeriTool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
9478 Retrascope RISC-V Benchmark Bug New Normal ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int' Sergey Smolov Actions
9012 Retrascope Test Suite Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
10290 Verilog Translator Feature New Normal SystemVerilog support Sergey Smolov Actions
10088 QEMU4V Feature New Low QEMU4V formatted traces for x86 programs Sergey Smolov Actions
3659 С++TESK Development Environment Task New Normal Соответствие полей классов сообщений и сигналов HDL-модели Sergey Smolov Actions
9888 Retrascope IDE Task New Normal complete migration from Ant to Gradle build system Sergey Smolov Retrascope IDE - 0.1 Actions
3755 С++TESK Development Environment Task New Normal namespace name for test system prototypes Sergey Smolov Actions
8167 QEMU4V Task New Low Program flow tracing Sergey Smolov Actions
3756 С++TESK Development Environment Task New Immediate Генерация C++ кода для модели сообщений Sergey Smolov Actions
3759 С++TESK Development Environment Task Feedback Normal Разработать демонстрационный пример для структуры соответствия Sergey Smolov Actions
9889 MicroTESK for Plasma Task Resolved Normal rm deprecated 'findbugs' plugin from Gradle build script Sergey Smolov Actions
9217 MicroTESK Task Closed Normal Use 'ru.ispras.castle.codegen' package classes from Castle Sergey Smolov Actions
7846 Fortress Task Rejected Normal 'Transformer.reduce(Transformer.substitute(expression, name, term))' convenience method Sergey Smolov Fortress - 0.4 Actions
10001 Fortress Task Rejected Normal SMT-LIBv2 benchmarks Sergey Smolov Actions
10082 Retrascope Bug New Normal WARNING: Illegal reflective access by org.python.core.PySystemState Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10191 Retrascope Bug Resolved Normal java.lang.IllegalArgumentException: Specified target vertex 0 is not part of graph Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10081 Retrascope Bug Resolved High tool hangs right after final "Duration: " msg Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9822 Verilog Translator Bug Resolved Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5836 Local Support Project Bug Resolved High не собирается проект на сервере Jenkins Sergey Smolov Sergey Smolov Actions
10075 Retrascope Bug Resolved Normal jython.jar: WARNING: An illegal reflective access operation has occurred at JDK 11 Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9848 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10174 Retrascope Bug Verified High nondeterminism at EFSM transitions generation Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10085 Retrascope Bug Closed Normal EfsmTransitionPropertyExtractorTestCase: There is no declaration of variable neither in this EFSM nor in its ancestors: process_0.D Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9075 Retrascope Bug Closed Normal java.lang.IllegalArgumentException: testNum 0 != 1 topModuleNum Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
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