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# Project Tracker Status Priority Subject Author Assignee Target version
9437 MicroTESK Bug Resolved Normal ru.ispras.microtesk.model.minimips.BufferPreparatorTestCase: QEMU4V crashes with general protection error on this test program Sergey Smolov MicroTESK - 2.4 Actions
9436 MicroTESK Bug New Normal ru.ispras.microtesk.mmu.translator.GeneralTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
9217 MicroTESK Task Closed Normal Use 'ru.ispras.castle.codegen' package classes from Castle Sergey Smolov Actions
9184 VeriTool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
9063 MicroTESK Bug New Normal microtesk/src/main/java/core/ru/ispras/microtesk/utils/PropertyMap.java uses unchecked or unsafe operations Sergey Smolov Actions
9012 Retrascope MC Benchmark Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
8167 QEMU4V Task New Low Program flow tracing Sergey Smolov Actions
7846 Fortress Task New Normal 'Transformer.reduce(Transformer.substitute(expression, name, term))' convenience method Sergey Smolov Fortress - 0.4 Actions
3759 С++TESK Development Environment Task Feedback Normal Разработать демонстрационный пример для структуры соответствия Sergey Smolov Actions
3756 С++TESK Development Environment Task New Immediate Генерация C++ кода для модели сообщений Sergey Smolov Actions
3755 С++TESK Development Environment Task New Normal namespace name for test system prototypes Sergey Smolov Actions
3659 С++TESK Development Environment Task New Normal Соответствие полей классов сообщений и сигналов HDL-модели Sergey Smolov Actions
9784 Verilog Translator Bug Resolved Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9771 Verilog Translator Task Resolved Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9769 Retrascope Feature Resolved Normal GraphML printers: make branch values italic Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9767 Retrascope Feature Resolved Normal GraphML printers: use dotted arrows for Module->(Module| Process) hierarchy dependencies Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9762 Retrascope Task Closed High prepare to 1.1.1 release Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9726 Retrascope MC Benchmark Task Closed Normal VerilogPrinter test cases Sergey Smolov Sergey Smolov Actions
9670 Retrascope MC Benchmark Task New Normal add 'ar.v' module to the test suite when SVA support will be implemented Sergey Smolov Sergey Smolov Actions
9607 Retrascope MC Benchmark Task Closed Normal add QUIP 9.0 benchmark Sergey Smolov Sergey Smolov Actions
9606 Retrascope MC Benchmark Task Closed Normal add IWLS 2005 benchmark Sergey Smolov Sergey Smolov Actions
9566 Retrascope MC Benchmark Task Closed Normal tests for Yosys-SMTBMC tool Sergey Smolov Sergey Smolov Actions
9565 Retrascope MC Benchmark Task Closed Normal tests for Verilog2SMV tool Sergey Smolov Sergey Smolov Actions
9564 Retrascope MC Benchmark Task Closed Normal tests for EBMC tool Sergey Smolov Sergey Smolov Actions
9488 Retrascope Task New Normal CFG-GADD transformer backend that makes assignments index and range-free Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
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