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# Project Tracker Status Priority Subject Author Assignee Target version
6108 MicroTESK Task Closed Normal create environment variable(s) for SMT solver(s) Sergey Smolov Andrei Tatarnikov MicroTESK - 2.2 Actions
5967 MicroTESK Task Closed Low one directory for all components of distribution Sergey Smolov Andrei Tatarnikov MicroTESK - 2.2 Actions
4674 TestBase Task New Normal Тестовые ситуации Sergey Smolov Artem Kotsynyak TestBase - 0.0 Actions
3914 Fortress Task Rejected Normal function templates Sergey Smolov Andrei Tatarnikov Fortress - 0.1 Actions
4133 Fortress Task Closed Normal ABS, MAX, MIN для Logic-типов Sergey Smolov Sergey Smolov Fortress - 0.1 Actions
3973 Fortress Task Closed Normal Реализовать добавление Variable в Constraint Sergey Smolov Sergey Smolov Fortress - 0.1 Actions
4175 Fortress Task Closed Normal Добавить параметризованные операции Sergey Smolov Sergey Smolov Fortress - 0.1 Actions
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8982 Verilog Translator Task New Normal "for" loop unrolling Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9859 Verilog Translator Task New Normal modify "ERROR: [Internal] null" line at error log Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9251 Verilog Translator Task Closed High calculate type of index for bit-vector arrays Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7725 Verilog Translator Task Closed Normal bitvector arrays support Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5455 Verilog Translator Task Closed Normal устранить зависимость от ANTLRWorks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9904 Verilog Translator Task Closed Normal add info for "--library-file" cmdline option Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9899 Verilog Translator Task Closed Normal VerilogPrinter test cases for QUIP benchmarks Sergey Smolov Maxim Chudnov Verilog Translator - 0.1 Actions
9232 Verilog Translator Task Closed High remove typedefs from texas97-tests/PPC60X_bus/src/define.v Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9207 Verilog Translator Task Closed Normal add VCEGAR benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9311 Verilog Translator Task Closed High type casting of expression operands Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10009 Verilog Translator Task Closed Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9206 Verilog Translator Task Closed Normal add Texas97 benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8205 Verilog Translator Task Closed Normal Gradle-based build environment Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5881 Verilog Translator Task Closed Normal keep file names in the AST top nodes Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7524 Verilog Translator Task Closed Normal support for non-zero-starting bit vector variables & signals Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9771 Verilog Translator Task Closed Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9208 Verilog Translator Task Closed Normal add Verilog2Smv\VIS benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5651 Verilog Translator Task Closed Normal Translate logic operation results into Boolean expressions Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5258 Retrascope Task Closed High [basis] Обработка циклических зависимостей разных Engine Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
4945 Retrascope Task Closed Normal [basis][log] Опция логирования Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
5249 Retrascope Task Closed High [basis] Настройка Retrascope для работы с SMT-решателями Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
4946 Retrascope Task Closed Normal [basis][log] Ведение лога для нескольких логгеров Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
5247 Retrascope Task Closed Normal [basis] Набор идентификаторов Engine как опция командной строки Retrascope Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
6354 Retrascope Task Closed Normal Collapsing group node for Module Sergey Smolov Alexander Protsenko Retrascope - 0.1 Actions
6049 Retrascope Task Closed Normal VHDL test printer: write documentation to project wiki Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5870 Retrascope Task Closed Normal Retrascope exceptions Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
6050 Retrascope Task Closed High Path to testbench directory as command-line parameter Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5501 Retrascope Task Closed Normal [efsm][generator][test] Class 'EfsmAtomicTestGenerator' is never used Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
4359 Retrascope Task Rejected Normal [cfg] Реализовать метод toConstraint() Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5498 Retrascope Task Closed Normal [model][basis][memory] rename IMemory interface Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5471 Retrascope Task Closed Normal [structure] Rename *ing packages Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5494 Retrascope Task Closed Normal [structure] remove ru.ispras.retrascope.engine.efsm.testgen.heuristic empty package Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5456 Retrascope Task Closed Normal [structure] Замечания по структуре каталогов Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5537 Retrascope Task Closed Normal [efsm][generator][test] make log shorter Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5495 Retrascope Task Closed Normal [structure] move ru.ispras.retrascope.testbench.media package to ru.ispras.retrascope.result.testbench Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5688 Retrascope Task Closed Normal implement test-to-VHDL printer Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5887 Retrascope Task Closed Normal rename 'decider_parser.vhd' Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5420 Retrascope Task Closed Normal [util] метод fillNodeWithValues заменить на Transformer.substituteAllBindings Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
6864 Retrascope Task Closed Normal Remove crypto-cores from test suite Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5578 Retrascope Task Closed Normal [verilog][parser][cfg] add support of multiple assignments Sergey Smolov Mikhail Chupilko Retrascope - 0.1 Actions
5398 Retrascope Task Closed Normal [verilog][parser][cfg] Преобразование констант в NodeValue Sergey Smolov Mikhail Chupilko Retrascope - 0.1 Actions
6367 Retrascope Task Closed Urgent Fortress expressions printing in an SMV format Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
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