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# Project Tracker Status Priority Subject Author Assignee Target version
3756 С++TESK Development Environment Task New Immediate Генерация C++ кода для модели сообщений Sergey Smolov Actions
9288 QEMU4V Bug Closed Immediate /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’ Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
9915 Verilog Translator Bug Verified Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9911 Retrascope Task Verified Urgent merge "*/sample/*TestCase" Java test cases Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
5680 Retrascope Bug Closed Urgent [efsm][generator][test][fate] DirectedFateGenerator.generateSequence -> NullPointerException Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5719 Retrascope Bug Closed Urgent EFSM Test Generator hangs on b11 Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
6367 Retrascope Task Closed Urgent Fortress expressions printing in an SMV format Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9993 Verilog Translator Bug New High if two modules are passed to the tool and one includes another, the tool hangs Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9764 Retrascope IDE Task New High migrate to Eclipse 2019 Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9670 Retrascope Test Suite Task New High add 'ar.v' module to the test suite when SVA support will be implemented Sergey Smolov Sergey Smolov Actions
4713 Fortress Task New High SMT-LIB structures Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
9247 Retrascope Feature Open High CFG-to-C printer Sergey Smolov Sergey Smolov Retrascope - 1.2 Actions
10081 Retrascope Bug Resolved High tool hangs right after final "Duration: " msg Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
5836 Local Support Project Bug Resolved High не собирается проект на сервере Jenkins Sergey Smolov Sergey Smolov Actions
10060 Retrascope Feature Resolved High Support SVA properties in CFG model Sergey Smolov Sergey Smolov Retrascope - 1.2 Actions
10102 MicroTESK Bug Verified High incorrect ld scripts for x86 test programs Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
10023 Retrascope Bug Verified High ru.ispras.retrascope.parser.verilog.VerilogParserTestCase: java.lang.Exception: Method runTest should have no parameters Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
10174 Retrascope Bug Verified High nondeterminism at EFSM transitions generation Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10173 Verilog Translator Bug Verified High javadoc: DefineStructure.java:37: warning: no @return Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10216 Verilog Translator Bug Verified High ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9962 Verilog Translator Bug Verified High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Verified High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10237 Verilog Translator Bug Verified High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9990 Verilog Translator Feature Verified High check for variable/net redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10139 Retrascope Task Verified High fix coding issues at *BenchTest classes Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
10073 Retrascope Task Verified High fix checkstyle warnings Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
9811 Verilog Translator Task Verified High macro with parameters Sergey Smolov Alexey Danilov Verilog Translator - 0.2 Actions
5873 Retrascope Bug Closed High missing transitions in b04 EFSM Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9296 Verilog Translator Bug Closed High vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9226 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9210 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.fortress.expression.Nodes.bvextract(Nodes.java:322) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5528 Retrascope Bug Closed High [engine][testbench] java.nio.file.FileAlreadyExistsException: decider_parser.vhd Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
6959 Retrascope IDE Bug Closed High java.lang.NullPointerException at startup Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
5525 Retrascope Bug Closed High [engine][xml] wrong package for TestXmlPrinterTestCase Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9224 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7730 MicroTESK Bug Closed High [tarmac-logger] missing "<cpu>" tag Sergey Smolov Andrei Tatarnikov MicroTESK - 2.4 Actions
9521 Retrascope Bug Closed High NuSMV works too slow on ITC'99 b11 design Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
6263 Retrascope Bug Closed High Crash when test generation engine elaborates EFSMs from alu.vhd: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5608 Retrascope Bug Closed High [efsm][generator][test][fate] FATE generator hangs at b03 description from ITC'99 Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5510 Retrascope Bug Closed High [efsm][generator][test] RandomFateSequenceIterator compilation error Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9386 MicroTESK for PowerPC Bug Closed High ru.ispras.microtesk.model.powerpc.InstructionALUTestCase: Assembler messages: ../microtesk-powerpc/build/test/instruction_alu/instruction_alu_0000.s:1: Error: junk at end of line, first unrecognized character is `/' Sergey Smolov Sergey Smolov Actions
5524 Retrascope Bug Closed High [engine][xml] wrong package for TestXmlPrinter Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5715 Retrascope Bug Closed High EfsmTestGenerator.java:138: error: method put in interface Map<K,V> cannot be applied to given types -> traversedPaths.put(efsm, new HashSet<>()); Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9222 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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