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# Project Tracker Status Priority Subject Author Assignee Target version
9904 Verilog Translator Task Verified Normal add info for "--library-file" cmdline option Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9477 Retrascope RISC-V Benchmark Bug New Normal an "import "DPI-C" function" construction causes Verilog Translator error Sergey Smolov Alexander Kamkin Actions
5096 Retrascope Bug Closed Normal [basis] FileCreator: "Can't create file" error Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
4946 Retrascope Task Closed Normal [basis][log] Ведение лога для нескольких логгеров Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
4945 Retrascope Task Closed Normal [basis][log] Опция логирования Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
5247 Retrascope Task Closed Normal [basis] Набор идентификаторов Engine как опция командной строки Retrascope Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
5249 Retrascope Task Closed High [basis] Настройка Retrascope для работы с SMT-решателями Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
5258 Retrascope Task Closed High [basis] Обработка циклических зависимостей разных Engine Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
7725 Verilog Translator Task Closed Normal bitvector arrays support Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9251 Verilog Translator Task Closed High calculate type of index for bit-vector arrays Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10069 MicroTESK Bug New Normal cpu.nml Error: Internal error: context [/Isa] 1:8 attribute file isn't defined Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
8738 Verilog Translator Bug Closed Normal DataMemTestCase falls with error Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10304 MicroTESK Task New Normal deprecation warnings via compilation Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
8681 Retrascope Bug Closed Normal EngineRegistry fails to create toolchain when HashSet\HashMap are used Sergey Smolov Alexander Kamkin Retrascope - 1.0 Actions
4702 Fortress Task Closed Normal [expression] Реализовать операцию BVBIT Sergey Smolov Alexander Kamkin Fortress - 0.3 Actions
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9594 Verilog Translator Bug Closed Normal extra 'BVEXTRACT' operation in right hand side expression in 'assign' block's statement Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9377 MicroTESK for MIPS Bug New Normal 'Failed to construct decoder' warnings in project's build log Sergey Smolov Alexander Kamkin Actions
8982 Verilog Translator Task New Normal "for" loop unrolling Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7564 MicroTESK Task Closed Normal "How to build MicroTESK" guide for developers in project Wiki Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
9993 Verilog Translator Bug New High if two modules are passed to the tool and one includes another, the tool hangs Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9173 Verilog Translator Bug Closed High Incorrect DataType: BIT_VECTOR(1) instead of BIT_VECTOR(40) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10102 MicroTESK Bug Verified High incorrect ld scripts for x86 test programs Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
9165 Verilog Translator Bug Closed High Incorrect parameter value calculation at hierarchical Verilog description Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9210 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.fortress.expression.Nodes.bvextract(Nodes.java:322) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9211 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8874 Verilog Translator Feature Closed High mapping from instance variables to their code entries Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9063 MicroTESK Bug Closed Normal microtesk/src/main/java/core/ru/ispras/microtesk/utils/PropertyMap.java uses unchecked or unsafe operations Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
8779 Verilog Translator Bug Closed Normal mips16/data_mem.v: wrong type for define-containing declaration of 'ram_addr' wire Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9859 Verilog Translator Task New Normal modify "ERROR: [Internal] null" line at error log Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9174 Verilog Translator Bug Closed High NullPointerException via VerilogLiteral construction Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10074 MicroTESK Feature New Normal option that stores boot obj at the generated ld script Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
9475 Retrascope RISC-V Benchmark Bug Closed Normal Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '(' Sergey Smolov Alexander Kamkin Actions
5526 Retrascope Task Rejected Normal Retrascope engines configuration Sergey Smolov Alexander Kamkin Actions
5492 Verilog Translator Bug Closed Normal retrascope + sapic.v = java.lang.IllegalStateException: Operand is not a constant integer value: 00000000000000000000000000000011 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9436 MicroTESK Bug Closed Normal ru.ispras.microtesk.mmu.translator.GeneralTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9282 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9190 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9160 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9182 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.MulFifoTestCase: java.lang.IllegalStateException: Parameter is not a value: i Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9803 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.MulFifoTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator$1.getNode(VerilogElaborator.java:932) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9202 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.PjIcuIcctl1TestCase: java.lang.ArrayIndexOutOfBoundsException: 3 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9775 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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