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# Project Tracker Status Priority Subject Author Assignee Target version
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9775 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9594 Verilog Translator Bug Open Normal extra 'BVEXTRACT' operation in right hand side expression in 'assign' block's statement Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9478 Retrascope RISC-V Benchmark Bug New Normal ru.ispras.verilog.parser.sample.RocketChipTestDriverVerilogPrinterTestCase: mismatched input 'unsigned' expecting LPAREN Sergey Smolov Alexander Kamkin Actions
9477 Retrascope RISC-V Benchmark Bug New Normal an "import "DPI-C" function" construction causes Verilog Translator error Sergey Smolov Alexander Kamkin Actions
9475 Retrascope RISC-V Benchmark Bug New Normal Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '(' Sergey Smolov Alexander Kamkin Actions
9377 MicroTESK for MIPS64 Bug New Normal 'Failed to construct decoder' warnings in project's build log Sergey Smolov Alexander Kamkin Actions
9376 MicroTESK for MIPS64 Bug New Normal Warning: Group MIPS64FpuOp contains two items add_fmt and mfc1 with the same opcode 01000100000000000000000000000000 Sergey Smolov Alexander Kamkin Actions
9296 Verilog Translator Bug Closed High vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9282 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug New High no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9251 Verilog Translator Task Closed High calculate type of index for bit-vector arrays Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9224 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9222 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9212 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9211 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9210 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.fortress.expression.Nodes.bvextract(Nodes.java:322) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9202 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.PjIcuIcctl1TestCase: java.lang.ArrayIndexOutOfBoundsException: 3 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9190 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9182 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.MulFifoTestCase: java.lang.IllegalStateException: Parameter is not a value: i Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9174 Verilog Translator Bug Closed High NullPointerException via VerilogLiteral construction Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9173 Verilog Translator Bug Closed High Incorrect DataType: BIT_VECTOR(1) instead of BIT_VECTOR(40) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9165 Verilog Translator Bug Closed High Incorrect parameter value calculation at hierarchical Verilog description Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9160 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9055 Verilog Translator Bug Closed High Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8990 Verilog Translator Bug Closed High vcegar-benchmarks/pi_bus/main_1.v: incorrect translation of nested "if" conditions Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8982 Verilog Translator Task New Normal "for" loop unrolling Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8957 Verilog Translator Bug Closed High wrong datatype for arrays Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8874 Verilog Translator Feature Closed High mapping from instance variables to their code entries Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8865 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_19_11_00_1: java.lang.IllegalArgumentException: Declaration=DECLARATION(), parent=MODULE(m2) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8864 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_17_10_02_1_i: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8863 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_17_02_04_4_1: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8862 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_08_02_1: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8861 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_03_1: java.lang.IllegalStateException: BigInteger data is not convertible to Boolean. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8860 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_02_4: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8859 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_02_3: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8858 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_01_2: java.lang.IllegalStateException: Parameter is not a value: (BVZEROEXT 2147483646 i) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8857 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_02_02_2_1: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8856 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_10_04_05_1: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8855 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_10_03_00_5: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8854 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_02_2: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8853 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8852 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_4: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8851 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_3: java.lang.IllegalArgumentException: 0 must be > 0 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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