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# Project Tracker Status Priority Subject Author Assignee Target version
3590 C++TESK Testing ToolKit Bug Closed Normal C++TesK installation fails on OpenSUSE 12.2 x64 Sergey Smolov Sergey Smolov C++TESK Testing ToolKit - 1.0 Actions
4005 C++TESK Testing ToolKit Bug Rejected Normal удалить пустой README Sergey Smolov asd ert C++TESK Testing ToolKit - 1.0 Actions
4004 C++TESK Testing ToolKit Bug Closed Normal Из build'а пропал скрипт install-eclipse-plugin.sh Sergey Smolov Sergey Smolov C++TESK Testing ToolKit - 1.0 Actions
6108 MicroTESK Task Closed Normal create environment variable(s) for SMT solver(s) Sergey Smolov Andrei Tatarnikov MicroTESK - 2.2 Actions
6106 MicroTESK Bug Closed Normal zero opcodes for instructions in Tarmac log Sergey Smolov Andrei Tatarnikov MicroTESK - 2.2 Actions
6241 MicroTESK Bug Closed Normal Generated assembler files contain tab-only lines Sergey Smolov Andrei Tatarnikov MicroTESK - 2.2 Actions
5967 MicroTESK Task Closed Low one directory for all components of distribution Sergey Smolov Andrei Tatarnikov MicroTESK - 2.2 Actions
7730 MicroTESK Bug Closed High [tarmac-logger] missing "<cpu>" tag Sergey Smolov Andrei Tatarnikov MicroTESK - 2.4 Actions
9437 MicroTESK Bug Closed Normal ru.ispras.microtesk.model.minimips.BufferPreparatorTestCase: QEMU4V crashes with general protection error on this test program Sergey Smolov Sergey Smolov MicroTESK - 2.4 Actions
4674 TestBase Task New Normal Тестовые ситуации Sergey Smolov Artem Kotsynyak TestBase - 0.0 Actions
10031 MicroTESK for PowerPC Bug New Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for PowerPC - 0.0 Actions
3973 Fortress Task Closed Normal Реализовать добавление Variable в Constraint Sergey Smolov Sergey Smolov Fortress - 0.1 Actions
4133 Fortress Task Closed Normal ABS, MAX, MIN для Logic-типов Sergey Smolov Sergey Smolov Fortress - 0.1 Actions
3914 Fortress Task Rejected Normal function templates Sergey Smolov Andrei Tatarnikov Fortress - 0.1 Actions
4175 Fortress Task Closed Normal Добавить параметризованные операции Sergey Smolov Sergey Smolov Fortress - 0.1 Actions
9915 Verilog Translator Bug Verified Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10173 Verilog Translator Bug Verified High javadoc: DefineStructure.java:37: warning: no @return Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Verified High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10237 Verilog Translator Bug Verified High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9990 Verilog Translator Feature Verified High check for variable/net redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10216 Verilog Translator Bug Verified High ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
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