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# Project Tracker Status Priority Subject Author Assignee Target version
9288 QEMU4V Bug Closed Immediate /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’ Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
9915 Verilog Translator Bug Closed Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
5719 Retrascope Bug Closed Urgent EFSM Test Generator hangs on b11 Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5680 Retrascope Bug Closed Urgent [efsm][generator][test][fate] DirectedFateGenerator.generateSequence -> NullPointerException Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9223 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_pj_icu_icctl1: ERROR: Declaration of 'clk' has not been found Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
5461 Fortress Bug Closed High [arrays] Insufficient arrays support Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
6959 Retrascope IDE Bug Closed High java.lang.NullPointerException at startup Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
6363 Verilog Translator Bug Closed High src/test/verilog/fifo0/mem_2p.v: AbstractMethodError Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8957 Verilog Translator Bug Closed High wrong datatype for arrays Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9190 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7730 MicroTESK Bug Closed High [tarmac-logger] missing "<cpu>" tag Sergey Smolov Andrei Tatarnikov MicroTESK - 2.4 Actions
10081 Retrascope Bug Resolved High tool hangs right after final "Duration: " msg Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
6352 Fortress Bug Closed High Transformer.standardize returns 'false' on (AND (EQ a 00) (NOT(EQ a b 00))) Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
10173 Verilog Translator Bug Closed High javadoc: DefineStructure.java:37: warning: no @return Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5453 Fortress Bug Closed High [arrays] Unexpected solver output: " (INSTQUEUE ((as const (Array Int Int)) 0))" Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
9993 Verilog Translator Bug New High if two modules are passed to the tool and one includes another, the tool hangs Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9210 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.fortress.expression.Nodes.bvextract(Nodes.java:322) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9174 Verilog Translator Bug Closed High NullPointerException via VerilogLiteral construction Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9165 Verilog Translator Bug Closed High Incorrect parameter value calculation at hierarchical Verilog description Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8786 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.FifoTestbenchTestCase fails Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10102 MicroTESK Bug Verified High incorrect ld scripts for x86 test programs Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
8990 Verilog Translator Bug Closed High vcegar-benchmarks/pi_bus/main_1.v: incorrect translation of nested "if" conditions Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9222 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10216 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Closed High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
6263 Retrascope Bug Closed High Crash when test generation engine elaborates EFSMs from alu.vhd: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5528 Retrascope Bug Closed High [engine][testbench] java.nio.file.FileAlreadyExistsException: decider_parser.vhd Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5425 Fortress Bug Closed High [expression] java.lang.IllegalArgumentException: Expression is not a condition: (BVEXTRACT D_IN 0 0) Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
10174 Retrascope Bug Verified High nondeterminism at EFSM transitions generation Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for '<var name>' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9962 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10023 Retrascope Bug Verified High ru.ispras.retrascope.parser.verilog.VerilogParserTestCase: java.lang.Exception: Method runTest should have no parameters Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
10237 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9296 Verilog Translator Bug Closed High vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9226 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9209 Verilog Translator Bug Closed High java.util.EmptyStackException at ru.ispras.verilog.parser.util.TokenSourceStack.getLastParentToken(TokenSourceStack.java:70) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9225 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_MPEG_prefixcode: ERROR: ../texas97-tests/MPEG/prefixcode.v line 70:8 no viable alternative at input ';' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9211 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9202 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.PjIcuIcctl1TestCase: java.lang.ArrayIndexOutOfBoundsException: 3 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9173 Verilog Translator Bug Closed High Incorrect DataType: BIT_VECTOR(1) instead of BIT_VECTOR(40) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9160 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5873 Retrascope Bug Closed High missing transitions in b04 EFSM Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5567 Verilog Translator Bug Closed High VerilogStaticChecker.ExpressionVisitor is not abstract and does not override abstract method getOperandOrder() in ExprTreeVisitor Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9282 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9521 Retrascope Bug Closed High NuSMV works too slow on ITC'99 b11 design Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9182 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.MulFifoTestCase: java.lang.IllegalStateException: Parameter is not a value: i Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9055 Verilog Translator Bug Closed High Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
4813 Fortress Bug Closed High [solver][constraint] Невозможно создавать тривиальные ограничения Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
9212 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5263 Retrascope Bug Rejected High [efsm][generator][test] EfsmTestGeneratorTestCase -> java.lang.OutOfMemoryError: Java heap space Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9224 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5510 Retrascope Bug Closed High [efsm][generator][test] RandomFateSequenceIterator compilation error Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5836 Local Support Project Bug Resolved High не собирается проект на сервере Jenkins Sergey Smolov Sergey Smolov Actions
9386 MicroTESK for PowerPC Bug Closed High ru.ispras.microtesk.model.powerpc.InstructionALUTestCase: Assembler messages: ../microtesk-powerpc/build/test/instruction_alu/instruction_alu_0000.s:1: Error: junk at end of line, first unrecognized character is `/' Sergey Smolov Sergey Smolov Actions
7557 Fortress Bug Closed High ConstCastTestCase: java.lang.AssertionError: Calculator failed to substitute result Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
5608 Retrascope Bug Closed High [efsm][generator][test][fate] FATE generator hangs at b03 description from ITC'99 Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
7423 Retrascope Bug Rejected High rnd_fsm.vhd: empty tst file Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
5524 Retrascope Bug Closed High [engine][xml] wrong package for TestXmlPrinter Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5525 Retrascope Bug Closed High [engine][xml] wrong package for TestXmlPrinterTestCase Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5648 Retrascope Bug Rejected High EfsmSimulator.executeAssignment -> Unsupported data type of ranged variable: (MAP LOGIC_INTEGER LOGIC_INTEGER) Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
6355 Verilog Translator Bug Closed High src/test/verilog/fifo/fifo_testbench.v: NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5715 Retrascope Bug Closed High EfsmTestGenerator.java:138: error: method put in interface Map<K,V> cannot be applied to given types -> traversedPaths.put(efsm, new HashSet<>()); Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
7097 Retrascope Bug Closed Normal 32-bit constants should be casted to appropriate values Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6892 Retrascope Bug Closed Normal support for non-zero starting bitvectors Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
9376 MicroTESK for MIPS Bug New Normal Warning: Group MIPS64FpuOp contains two items add_fmt and mfc1 with the same opcode 01000100000000000000000000000000 Sergey Smolov Alexander Kamkin Actions
9387 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.InstructionBPUTestCase: ../microtesk-powerpc/build/test/instruction_bpu/instruction_bpu_0000.s:47: Error: operand out of range (0x0000000000002774 is not between 0x0000000000000000 and 0x000000000000001 Sergey Smolov Alexander Protsenko Actions
8283 Retrascope Bug Closed Normal "X <= (others => '0')" should be translated properly when X is bit vector Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6443 Retrascope Bug Closed Normal print error message when "--toplevel" value is wrong Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6424 Retrascope Bug Closed Normal b05.vhd: line 64: at token "d32_-10": syntax error Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
9375 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.GroupTestCase: org.jruby.exceptions.RaiseException: (NoMethodError) undefined method `la' for #<GroupGenTemplate:0x6046f0da> Sergey Smolov Alexander Protsenko Actions
6279 Retrascope Bug Closed Normal TestXmlPrinterTestCase: IllegalArgumentException: Output file name isn't specified Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9374 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.BoundaryTestCase: Simulation failedThe CPR storage is not defined in the model.ru.ispras.microtesk.model.ConfigurationException: The CPR storage is not defined in the model. Sergey Smolov Alexander Protsenko Actions
10370 Fortress Bug Closed Normal class ru.ispras.fortress.solver.constraint.Formulas cannot be cast to class ru.ispras.fortress.solver.constraint.Sat4jFormula Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
10094 MicroTESK Bug Verified Normal strange common code at LinkerScript.stg Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
8245 Retrascope Bug Closed Normal cfg-rnd-testgen: IllegalArgumentException at minimips\pps_pf.v Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6362 Retrascope Bug Rejected Normal src/test/verilog/adder/adder4_testbench.v: wrong CFG model Sergey Smolov Mikhail Chupilko Retrascope - 0.1 Actions
10069 MicroTESK Bug New Normal cpu.nml Error: Internal error: context [/Isa] 1:8 attribute file isn't defined Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
10031 MicroTESK for PowerPC Bug New Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for PowerPC - 0.0 Actions
9436 MicroTESK Bug Closed Normal ru.ispras.microtesk.mmu.translator.GeneralTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
9012 Retrascope Test Suite Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
9176 Retrascope Test Suite Bug Closed Normal VcegarHlddSmvPrinterTestCase: java.lang.IllegalArgumentException: Unknown operation 'BVSDIV' Sergey Smolov Mikhail Lebedev Actions
9477 Retrascope RISC-V Benchmark Bug New Normal an "import "DPI-C" function" construction causes Verilog Translator error Sergey Smolov Alexander Kamkin Actions
6426 Retrascope Bug Closed Normal example.vhd: HlddXmvVisitor.onProcessEnd(HlddXmvVisitor.java:381) -> NullPointerException Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
9172 Retrascope Test Suite Bug Closed Normal Texas97ParsepackCfgGraphMlTestCase: ru.ispras.retrascope.basis.exception.RetrascopeException: Wrong range: 0 < 0 or 7 > 1. Sergey Smolov Sergey Smolov Actions
6504 Retrascope Bug Closed Normal fifo/fifo.v: nuSMV model checker returns ERROR Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
6730 Retrascope Bug Closed Normal fix javadoc Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
5401 Fortress Bug Closed Normal error at ru/ispras/fortress/solver/constraint/ArrayTestCase.java Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
9011 Retrascope Test Suite Bug Closed Normal Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Sergey Smolov Actions
9482 Retrascope RISC-V Benchmark Bug Closed Normal ru.ispras.retrascope.sample.VexRiscvVexRiscvGaddTestCase: ERROR: Wrong number of out edges for 'ru.ispras.retrascope.model.cfg.CfgBlockStatement@c219bf5': 2 Sergey Smolov Sergey Smolov Actions
9175 Retrascope Test Suite Bug Closed Normal Texas97PdlxCfgGraphMlTestCase: NullPointerException Sergey Smolov Sergey Smolov Actions
9475 Retrascope RISC-V Benchmark Bug Closed Normal Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '(' Sergey Smolov Alexander Kamkin Actions
6425 Retrascope Bug Closed Normal b12.vhd: XmvExprPrinter.getConstant(XmvExprPrinter.java:330) -> NullPointerException Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
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