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# Project Tracker Status Priority Subject Author Assignee Target version
10513 Verilog Translator Bug New Normal macOS related line endings at Verilog modules Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10512 Verilog Translator Bug New Normal ADDA162H90A_atop.v line 120:47 mismatched input ':' expecting RPAREN Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10510 Verilog Translator Bug New Normal ERROR: [Internal] Bit vector sizes do not match: 32 != 2. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10509 Verilog Translator Bug New Normal ERROR: [Internal] 0 must be > 0 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10508 Verilog Translator Bug New Normal ERROR: [Internal] Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10505 Verilog Translator Bug New Normal ERROR: [Internal] 11 must be within range [0, 1) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10502 Verilog Translator Bug New Normal subbytes.v line 76:13 no viable alternative at input '[' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10382 Verilog Translator Bug Closed Normal java.lang.IllegalArgumentException: expression=(BVREPEAT test.uut._saxi_maskwidth 1) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10370 Fortress Bug Closed Normal class ru.ispras.fortress.solver.constraint.Formulas cannot be cast to class ru.ispras.fortress.solver.constraint.Sat4jFormula Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
10289 Retrascope Bug Verified Normal ru.ispras.retrascope.engine.hldd.printer.smv.property.HlddPropertySmvPrinterTestCase.runTest: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Mikhail Lebedev Retrascope - 1.1 Actions
10266 Retrascope Bug Verified Normal ru.ispras.retrascope.engine.hldd.printer.smv.HlddSmvPrinterTestCase.runTest: java.lang.NullPointerException Sergey Smolov Mikhail Lebedev Retrascope - 1.1 Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10245 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_pci_wbw_wbr_fifos: ERROR: [Internal] null Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10241 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_dctub_jpeg: ERROR: ..\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 1:70 mismatched character '\r' expecting '\n' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10237 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10236 Retrascope Bug Rejected Normal efsm-test-generator hangs at opencores/mips16/data_mem.v Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10216 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10215 Verilog Translator Bug New Normal ERROR: Starting points limit has been exhausted: 2255 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10202 Verilog Translator Bug Closed Normal SVA grammar warnings via assembling Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
10191 Retrascope Bug Resolved Normal java.lang.IllegalArgumentException: Specified target vertex 0 is not part of graph Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10174 Retrascope Bug Verified High nondeterminism at EFSM transitions generation Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10173 Verilog Translator Bug Closed High javadoc: DefineStructure.java:37: warning: no @return Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10141 Verilog Translator Bug Closed Normal check port redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10131 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10121 MicroTESK Bug Open Normal technical output printing at 'compile.sh' script running with '--help' option Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
10102 MicroTESK Bug Verified High incorrect ld scripts for x86 test programs Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
10094 MicroTESK Bug Verified Normal strange common code at LinkerScript.stg Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
10085 Retrascope Bug Closed Normal EfsmTransitionPropertyExtractorTestCase: There is no declaration of variable neither in this EFSM nor in its ancestors: process_0.D Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10082 Retrascope Bug New Normal WARNING: Illegal reflective access by org.python.core.PySystemState Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10081 Retrascope Bug Resolved High tool hangs right after final "Duration: " msg Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10075 Retrascope Bug Resolved Normal jython.jar: WARNING: An illegal reflective access operation has occurred at JDK 11 Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10069 MicroTESK Bug New Normal cpu.nml Error: Internal error: context [/Isa] 1:8 attribute file isn't defined Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
10041 QEMU4V Bug Closed Normal wrong names for PowerPC registers in trace Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
10031 MicroTESK for PowerPC Bug New Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for PowerPC - 0.0 Actions
10023 Retrascope Bug Verified High ru.ispras.retrascope.parser.verilog.VerilogParserTestCase: java.lang.Exception: Method runTest should have no parameters Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
9993 Verilog Translator Bug New High if two modules are passed to the tool and one includes another, the tool hangs Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9962 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Closed High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9915 Verilog Translator Bug Closed Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for '<var name>' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9901 Retrascope Test Suite Bug New Low initializationError in some tests after Jenkins update Sergey Smolov Mikhail Lebedev Actions
9892 MicroTESK for RISC-V Bug Closed Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for RISC-V - 0.1 Actions
9848 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9844 Retrascope Test Suite Bug Rejected Normal Bash scripts that run side tools (EBMC, SymbiYosys, Verilog2SMV) can't extract names of several Verilog modules Sergey Smolov Sergey Smolov Actions
9822 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9816 Retrascope IDE Bug New Normal Retrascope IDE does not appear in "Installed Software" menu Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9803 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.MulFifoTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator$1.getNode(VerilogElaborator.java:932) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9784 Verilog Translator Bug Closed Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9775 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9763 Retrascope Test Suite Bug Closed Normal missing javadoc headers in Java files of 'ru.ispras.retrascope.engine.hldd.printer.smv.spec.sample.vcegar' package Sergey Smolov Mikhail Lebedev Actions
9594 Verilog Translator Bug Closed Normal extra 'BVEXTRACT' operation in right hand side expression in 'assign' block's statement Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9562 Retrascope Bug Closed Normal ru.ispras.retrascope.engine.hldd.printer.smv.usedef.MemStageUseDefSmvPrinterTestCase: model checker crashes without errors in *.smvlog Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9521 Retrascope Bug Closed High NuSMV works too slow on ITC'99 b11 design Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9485 Retrascope Bug Closed Normal missing javadoc Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9482 Retrascope RISC-V Benchmark Bug Closed Normal ru.ispras.retrascope.sample.VexRiscvVexRiscvGaddTestCase: ERROR: Wrong number of out edges for 'ru.ispras.retrascope.model.cfg.CfgBlockStatement@c219bf5': 2 Sergey Smolov Sergey Smolov Actions
9478 Retrascope RISC-V Benchmark Bug New Normal ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int' Sergey Smolov Actions
9477 Retrascope RISC-V Benchmark Bug New Normal an "import "DPI-C" function" construction causes Verilog Translator error Sergey Smolov Alexander Kamkin Actions
9475 Retrascope RISC-V Benchmark Bug Closed Normal Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '(' Sergey Smolov Alexander Kamkin Actions
9463 Retrascope Bug Closed Normal check if jUnit test cases for CfgCgaaTransformer return same results on different machines\platforms Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9437 MicroTESK Bug Closed Normal ru.ispras.microtesk.model.minimips.BufferPreparatorTestCase: QEMU4V crashes with general protection error on this test program Sergey Smolov Sergey Smolov MicroTESK - 2.4 Actions
9436 MicroTESK Bug Closed Normal ru.ispras.microtesk.mmu.translator.GeneralTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
9387 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.InstructionBPUTestCase: ../microtesk-powerpc/build/test/instruction_bpu/instruction_bpu_0000.s:47: Error: operand out of range (0x0000000000002774 is not between 0x0000000000000000 and 0x000000000000001 Sergey Smolov Alexander Protsenko Actions
9386 MicroTESK for PowerPC Bug Closed High ru.ispras.microtesk.model.powerpc.InstructionALUTestCase: Assembler messages: ../microtesk-powerpc/build/test/instruction_alu/instruction_alu_0000.s:1: Error: junk at end of line, first unrecognized character is `/' Sergey Smolov Sergey Smolov Actions
9377 MicroTESK for MIPS Bug New Normal 'Failed to construct decoder' warnings in project's build log Sergey Smolov Alexander Kamkin Actions
9376 MicroTESK for MIPS Bug New Normal Warning: Group MIPS64FpuOp contains two items add_fmt and mfc1 with the same opcode 01000100000000000000000000000000 Sergey Smolov Alexander Kamkin Actions
9375 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.GroupTestCase: org.jruby.exceptions.RaiseException: (NoMethodError) undefined method `la' for #<GroupGenTemplate:0x6046f0da> Sergey Smolov Alexander Protsenko Actions
9374 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.BoundaryTestCase: Simulation failedThe CPR storage is not defined in the model.ru.ispras.microtesk.model.ConfigurationException: The CPR storage is not defined in the model. Sergey Smolov Alexander Protsenko Actions
9365 QEMU4V Bug Closed Normal missing insn binary images in MIPS trace Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9334 QEMU4V Bug Closed Normal timestamp reset at MIPS trace Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9333 QEMU4V Bug Closed Normal unexpected hex value in MIPS trace Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9309 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.engine.smv.testbench.sample.vcegar.VcegarPiBusAssertSmvTestbenchTestCase:line 2 column 34: invalid declaration, builtin symbol select Sergey Smolov Sergey Smolov Actions
9296 Verilog Translator Bug Closed High vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9288 QEMU4V Bug Closed Immediate /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’ Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
9282 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9226 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9225 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_MPEG_prefixcode: ERROR: ../texas97-tests/MPEG/prefixcode.v line 70:8 no viable alternative at input ';' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9224 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9223 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_pj_icu_icctl1: ERROR: Declaration of 'clk' has not been found Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9222 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9212 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9211 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9210 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.fortress.expression.Nodes.bvextract(Nodes.java:322) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9209 Verilog Translator Bug Closed High java.util.EmptyStackException at ru.ispras.verilog.parser.util.TokenSourceStack.getLastParentToken(TokenSourceStack.java:70) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9203 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.basis.HlddAssertSmvTestbenchBenchmarkTest.runTest: java.lang.IllegalArgumentException: 'benchmarks' field is not initialized. Sergey Smolov Mikhail Lebedev Actions
9202 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.PjIcuIcctl1TestCase: java.lang.ArrayIndexOutOfBoundsException: 3 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9190 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9184 Veritool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
9182 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.MulFifoTestCase: java.lang.IllegalStateException: Parameter is not a value: i Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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