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# Project Tracker Status Priority Subject Author Assignee Target version
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7423 Retrascope Bug Rejected High rnd_fsm.vhd: empty tst file Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
6808 Retrascope Task Rejected High Split CFG processes into independent parts Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5648 Retrascope Bug Rejected High EfsmSimulator.executeAssignment -> Unsupported data type of ranged variable: (MAP LOGIC_INTEGER LOGIC_INTEGER) Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
5263 Retrascope Bug Rejected High [efsm][generator][test] EfsmTestGeneratorTestCase -> java.lang.OutOfMemoryError: Java heap space Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10236 Retrascope Bug Rejected Normal efsm-test-generator hangs at opencores/mips16/data_mem.v Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10059 Retrascope Task Rejected Normal mv all the project tests to JUnit 5 platform Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
10001 Fortress Task Rejected Normal SMT-LIBv2 benchmarks Sergey Smolov Actions
9844 Retrascope Test Suite Bug Rejected Normal Bash scripts that run side tools (EBMC, SymbiYosys, Verilog2SMV) can't extract names of several Verilog modules Sergey Smolov Sergey Smolov Actions
9839 Retrascope Test Suite Task Rejected Normal scripts for commercial FV tools running Sergey Smolov Sergey Smolov Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8304 Retrascope Feature Rejected Normal SLR values number limit Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7846 Fortress Task Rejected Normal 'Transformer.reduce(Transformer.substitute(expression, name, term))' convenience method Sergey Smolov Fortress - 0.4 Actions
7723 Retrascope Task Rejected Normal Support for module instances in Verilog descriptions Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
7594 Retrascope Bug Rejected Normal ModelSim shows error when TST file contains multiple comments Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7081 Retrascope Task Rejected Normal xor-composition-printer Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6990 Retrascope IDE Task Rejected Normal use veditor 1.2.1c Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
6989 Retrascope IDE Task Rejected Normal migrate to Eclipse Mars (4.5) Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
6511 Retrascope Task Rejected Normal keep expressions at case statements Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6509 Retrascope Task Rejected Normal merge embedded switch nodes with conditions depending exactly from the same variable(s) Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6412 Retrascope Task Rejected Normal engine combining HLDD & assertion model Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6393 Retrascope Task Rejected Normal migrate to EFSM model containing only concurrent assignments Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
6366 Retrascope Bug Rejected Normal src/test/vhdl/example/test.vhd: Efsm.UNINITIALISED_STATE isn't supported yet Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
6362 Retrascope Bug Rejected Normal src/test/verilog/adder/adder4_testbench.v: wrong CFG model Sergey Smolov Mikhail Chupilko Retrascope - 0.1 Actions
5692 Retrascope Bug Rejected Normal FATE/FATE+ hangs on b03 with Java 1.8 Sergey Smolov Igor Melnichenko Actions
5609 Retrascope Task Rejected Normal make process-local variables be efsm-model-global Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5526 Retrascope Task Rejected Normal Retrascope engines configuration Sergey Smolov Alexander Kamkin Actions
5507 Retrascope Task Rejected Normal [engine][basis] implement PrinterEngine Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5320 Retrascope Task Rejected Normal [cfg] Методы копирования вершин CFG Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5259 Fortress Task Rejected Normal [build] удаление папки distr при выполнении команды ant clean Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
5127 Retrascope IDE Task Rejected Normal [cfg][printer][graphml] Интегрировать плагин для yEd Sergey Smolov Alexander Protsenko Actions
5004 Retrascope Bug Rejected Normal [efsm][simulator][execution] ReferenceEfsmTestGeneratorTest.java : java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5003 Retrascope Bug Rejected Normal [util] XmlUtilTest.java: java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
4971 Retrascope Task Rejected Normal [model][basis] AssignAtomicStatement vs Binding Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4929 Retrascope Task Rejected Normal [cfg][model] Добавить структуру данных для представления задержек (delay) в присваиваниях Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
4928 Retrascope Bug Rejected Normal [cfg] Range может состоять из нескольких участков Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4927 Retrascope Task Rejected Normal [cfg][model] Убрать узел типа ASSERT Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4359 Retrascope Task Rejected Normal [cfg] Реализовать метод toConstraint() Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
4005 C++TESK Testing ToolKit Bug Rejected Normal удалить пустой README Sergey Smolov asd ert C++TESK Testing ToolKit - 1.0 Actions
3914 Fortress Task Rejected Normal function templates Sergey Smolov Andrei Tatarnikov Fortress - 0.1 Actions
3605 Retrascope Bug Rejected Normal [vhdl][parser][cfg] Zamia не обрабатывает пакеты функций Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6423 Fortress Task Rejected Low to_real, to_int, is_int operations Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
6364 Fortress Task Rejected Low SolverResult: implement equals\hashcode methods Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
5684 Retrascope Bug Rejected Low computeExpression -> LOGIC_BOOLEAN vs (MAP LOGIC_INTEGER LOGIC_BOOLEAN) Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
9288 QEMU4V Bug Closed Immediate /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’ Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
9915 Verilog Translator Bug Closed Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
6367 Retrascope Task Closed Urgent Fortress expressions printing in an SMV format Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
5719 Retrascope Bug Closed Urgent EFSM Test Generator hangs on b11 Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5680 Retrascope Bug Closed Urgent [efsm][generator][test][fate] DirectedFateGenerator.generateSequence -> NullPointerException Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
10237 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10216 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10173 Verilog Translator Bug Closed High javadoc: DefineStructure.java:37: warning: no @return Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9990 Verilog Translator Feature Closed High check for variable/net redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9962 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Closed High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9811 Verilog Translator Task Closed High macro with parameters Sergey Smolov Alexey Danilov Verilog Translator - 0.2 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9766 Retrascope Task Closed High remove 'vhdl.record' Git branch from remote repo Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
9762 Retrascope Task Closed High prepare to 1.1.1 release Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9521 Retrascope Bug Closed High NuSMV works too slow on ITC'99 b11 design Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9386 MicroTESK for PowerPC Bug Closed High ru.ispras.microtesk.model.powerpc.InstructionALUTestCase: Assembler messages: ../microtesk-powerpc/build/test/instruction_alu/instruction_alu_0000.s:1: Error: junk at end of line, first unrecognized character is `/' Sergey Smolov Sergey Smolov Actions
9311 Verilog Translator Task Closed High type casting of expression operands Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9296 Verilog Translator Bug Closed High vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9282 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9277 Retrascope Task Closed High mv clock-like variable detection to CFG-to-CGAA transformer Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9251 Verilog Translator Task Closed High calculate type of index for bit-vector arrays Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9248 Retrascope Task Closed High CFG model process should not have it's own internal variables Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9242 Retrascope Task Closed High check BVEXTRACT operation's parameter order Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9232 Verilog Translator Task Closed High remove typedefs from texas97-tests/PPC60X_bus/src/define.v Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9227 Retrascope Feature Closed High support for 'BVEXTRACT(x y (SELECT z w))' constructions in left hand sides of assigments Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9226 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9225 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_MPEG_prefixcode: ERROR: ../texas97-tests/MPEG/prefixcode.v line 70:8 no viable alternative at input ';' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9224 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9223 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_pj_icu_icctl1: ERROR: Declaration of 'clk' has not been found Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9222 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9212 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9211 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9210 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.fortress.expression.Nodes.bvextract(Nodes.java:322) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9209 Verilog Translator Bug Closed High java.util.EmptyStackException at ru.ispras.verilog.parser.util.TokenSourceStack.getLastParentToken(TokenSourceStack.java:70) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9202 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.PjIcuIcctl1TestCase: java.lang.ArrayIndexOutOfBoundsException: 3 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9190 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9182 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.MulFifoTestCase: java.lang.IllegalStateException: Parameter is not a value: i Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9174 Verilog Translator Bug Closed High NullPointerException via VerilogLiteral construction Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9173 Verilog Translator Bug Closed High Incorrect DataType: BIT_VECTOR(1) instead of BIT_VECTOR(40) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9165 Verilog Translator Bug Closed High Incorrect parameter value calculation at hierarchical Verilog description Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9160 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9123 Fortress Feature Closed High calculate DataType for 'BVEXTRACT(i, i, x)' NodeOperation objects Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
9055 Verilog Translator Bug Closed High Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8990 Verilog Translator Bug Closed High vcegar-benchmarks/pi_bus/main_1.v: incorrect translation of nested "if" conditions Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8957 Verilog Translator Bug Closed High wrong datatype for arrays Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8874 Verilog Translator Feature Closed High mapping from instance variables to their code entries Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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