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# Project Tracker Status Priority Subject Author Assignee Target version
9771 Verilog Translator Task Closed Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
3721 Fortress Task Closed Normal Дополнительные операции Sergey Smolov Sergey Smolov Actions
3708 Fortress Task Closed Normal Методы makeNegation, makeConjunction, makeDisjunction класса Constraint Sergey Smolov Sergey Smolov Actions
9415 QEMU4V Task Closed Normal migrate to QEMU 3.1.0 Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
9363 QEMU4V Task Closed Normal remove 'set_q4v_tstamp' function calls from RISC-V/MIPS/Aarch64 'cpu_loop.c' modules Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9311 Verilog Translator Task Closed High type casting of expression operands Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8432 Trace Matcher Task Closed Normal register records: register names can contain all but space symbols Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
9208 Verilog Translator Task Closed Normal add Verilog2Smv\VIS benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9207 Verilog Translator Task Closed Normal add VCEGAR benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9206 Verilog Translator Task Closed Normal add Texas97 benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8184 Trace Matcher Task Closed Normal compare record fields in case insensitive mode Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10492 Fortress Task Closed Normal use CVC4 1.8 in testing Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
4924 Retrascope Task Closed Normal [cfg][model] Представление непрерывных присваиваний Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
8181 Trace Matcher Task Closed Normal check whether trace records are ordered by time Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8179 Trace Matcher Task Closed Normal ChangeLog Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
9564 Retrascope Test Suite Task Closed Normal tests for EBMC tool Sergey Smolov Sergey Smolov Actions
9565 Retrascope Test Suite Task Closed Normal tests for Verilog2SMV tool Sergey Smolov Sergey Smolov Actions
9566 Retrascope Test Suite Task Closed Normal tests for Yosys-SMTBMC tool Sergey Smolov Sergey Smolov Actions
9606 Retrascope Test Suite Task Closed Normal add IWLS 2005 benchmark Sergey Smolov Sergey Smolov Actions
9607 Retrascope Test Suite Task Closed Normal add QUIP 9.0 benchmark Sergey Smolov Sergey Smolov Actions
9726 Retrascope Test Suite Task Closed Normal VerilogPrinter test cases Sergey Smolov Sergey Smolov Actions
8161 Trace Matcher Task Closed Normal Basic modules Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
7524 Verilog Translator Task Closed Normal support for non-zero-starting bit vector variables & signals Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5881 Verilog Translator Task Closed Normal keep file names in the AST top nodes Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5651 Verilog Translator Task Closed Normal Translate logic operation results into Boolean expressions Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8113 Trace Matcher Task Closed Normal Gradle build environment Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
7733 Trace Matcher Task Closed Normal run.bat script for Windows Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
7732 Trace Matcher Task Closed Normal oracle: record queue based comparison approach Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
7663 Trace Matcher Task Closed Normal "main" function Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10018 Trace Matcher Task Closed Normal migrate to Python 3 Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10017 Trace Matcher Task Closed Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10016 Trace Matcher Task Closed Normal Use Gradle 4.10.3 in build system Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
9269 QEMU4V Task Closed Normal migrate to QEMU 3.0.0 Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
4558 Retrascope Task Closed Normal [cfg][model] Реализовать обходчик для внутреннего представления описаний аппаратуры Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4580 Retrascope Task Closed Normal Поместить проект MiniMIPS в share/vhdl Sergey Smolov Sergey Smolov Actions
4807 Retrascope Task Closed Normal Action as interface for BasicBlock, Assertion, Situation Sergey Smolov Sergey Smolov Actions
4829 Retrascope Task Closed Normal [cfg][transformer][cgaa] CFG: Assertion building Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9012 Retrascope Test Suite Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
9217 MicroTESK Task Closed Normal Use 'ru.ispras.castle.codegen' package classes from Castle Sergey Smolov Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5526 Retrascope Task Rejected Normal Retrascope engines configuration Sergey Smolov Alexander Kamkin Actions
5127 Retrascope IDE Task Rejected Normal [cfg][printer][graphml] Интегрировать плагин для yEd Sergey Smolov Alexander Protsenko Actions
6364 Fortress Task Rejected Low SolverResult: implement equals\hashcode methods Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
3914 Fortress Task Rejected Normal function templates Sergey Smolov Andrei Tatarnikov Fortress - 0.1 Actions
5259 Fortress Task Rejected Normal [build] удаление папки distr при выполнении команды ant clean Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
6423 Fortress Task Rejected Low to_real, to_int, is_int operations Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
4005 C++TESK Testing ToolKit Bug Rejected Normal удалить пустой README Sergey Smolov asd ert C++TESK Testing ToolKit - 1.0 Actions
5003 Retrascope Bug Rejected Normal [util] XmlUtilTest.java: java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5004 Retrascope Bug Rejected Normal [efsm][simulator][execution] ReferenceEfsmTestGeneratorTest.java : java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5263 Retrascope Bug Rejected High [efsm][generator][test] EfsmTestGeneratorTestCase -> java.lang.OutOfMemoryError: Java heap space Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
7423 Retrascope Bug Rejected High rnd_fsm.vhd: empty tst file Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
6366 Retrascope Bug Rejected Normal src/test/vhdl/example/test.vhd: Efsm.UNINITIALISED_STATE isn't supported yet Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
5692 Retrascope Bug Rejected Normal FATE/FATE+ hangs on b03 with Java 1.8 Sergey Smolov Igor Melnichenko Actions
5684 Retrascope Bug Rejected Low computeExpression -> LOGIC_BOOLEAN vs (MAP LOGIC_INTEGER LOGIC_BOOLEAN) Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
5648 Retrascope Bug Rejected High EfsmSimulator.executeAssignment -> Unsupported data type of ranged variable: (MAP LOGIC_INTEGER LOGIC_INTEGER) Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
4359 Retrascope Task Rejected Normal [cfg] Реализовать метод toConstraint() Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
6393 Retrascope Task Rejected Normal migrate to EFSM model containing only concurrent assignments Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
10059 Retrascope Task Rejected Normal mv all the project tests to JUnit 5 platform Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
6362 Retrascope Bug Rejected Normal src/test/verilog/adder/adder4_testbench.v: wrong CFG model Sergey Smolov Mikhail Chupilko Retrascope - 0.1 Actions
9844 Retrascope Test Suite Bug Rejected Normal Bash scripts that run side tools (EBMC, SymbiYosys, Verilog2SMV) can't extract names of several Verilog modules Sergey Smolov Sergey Smolov Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7594 Retrascope Bug Rejected Normal ModelSim shows error when TST file contains multiple comments Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
3605 Retrascope Bug Rejected Normal [vhdl][parser][cfg] Zamia не обрабатывает пакеты функций Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
10236 Retrascope Bug Rejected Normal efsm-test-generator hangs at opencores/mips16/data_mem.v Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
4928 Retrascope Bug Rejected Normal [cfg] Range может состоять из нескольких участков Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
8304 Retrascope Feature Rejected Normal SLR values number limit Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
4971 Retrascope Task Rejected Normal [model][basis] AssignAtomicStatement vs Binding Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6990 Retrascope IDE Task Rejected Normal use veditor 1.2.1c Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
7723 Retrascope Task Rejected Normal Support for module instances in Verilog descriptions Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
6989 Retrascope IDE Task Rejected Normal migrate to Eclipse Mars (4.5) Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
5609 Retrascope Task Rejected Normal make process-local variables be efsm-model-global Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9839 Retrascope Test Suite Task Rejected Normal scripts for commercial FV tools running Sergey Smolov Sergey Smolov Actions
4929 Retrascope Task Rejected Normal [cfg][model] Добавить структуру данных для представления задержек (delay) в присваиваниях Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7081 Retrascope Task Rejected Normal xor-composition-printer Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5320 Retrascope Task Rejected Normal [cfg] Методы копирования вершин CFG Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6511 Retrascope Task Rejected Normal keep expressions at case statements Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6412 Retrascope Task Rejected Normal engine combining HLDD & assertion model Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4927 Retrascope Task Rejected Normal [cfg][model] Убрать узел типа ASSERT Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6509 Retrascope Task Rejected Normal merge embedded switch nodes with conditions depending exactly from the same variable(s) Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5507 Retrascope Task Rejected Normal [engine][basis] implement PrinterEngine Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6808 Retrascope Task Rejected High Split CFG processes into independent parts Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7846 Fortress Task Rejected Normal 'Transformer.reduce(Transformer.substitute(expression, name, term))' convenience method Sergey Smolov Fortress - 0.4 Actions
10001 Fortress Task Rejected Normal SMT-LIBv2 benchmarks Sergey Smolov Actions
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