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# Project Tracker Status Priority Subject Author Assignee Target version
6355 Verilog Translator Bug Closed High src/test/verilog/fifo/fifo_testbench.v: NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7098 Verilog Translator Bug Closed Normal src/test/verilog/mips16/data_mem.v: 'mem_access_addr' has null declaration Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
6365 Retrascope Bug Closed Normal src/test/vhdl/example/example.vhd: IllegalArgumentException Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
6366 Retrascope Bug Rejected Normal src/test/vhdl/example/test.vhd: Efsm.UNINITIALISED_STATE isn't supported yet Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
10099 Trace Matcher Feature Resolved Normal "--start-addr <hex value>" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
6051 Retrascope Task Closed Normal state-like variable names option Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6453 Retrascope Task Closed Normal Statement class for grouping CFG nodes Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5861 Fortress Task Closed Low static boolean containsSingleObject(Collection<?> collection) Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
5683 Retrascope Task Closed Normal STD_LOGIC/STD_ULOGIC processing Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
10094 MicroTESK Bug Verified Normal strange common code at LinkerScript.stg Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
5495 Retrascope Task Closed Normal [structure] move ru.ispras.retrascope.testbench.media package to ru.ispras.retrascope.result.testbench Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5481 Retrascope Task Closed Normal [structure] remove raw packages from main build folder Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5494 Retrascope Task Closed Normal [structure] remove ru.ispras.retrascope.engine.efsm.testgen.heuristic empty package Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5471 Retrascope Task Closed Normal [structure] Rename *ing packages Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5456 Retrascope Task Closed Normal [structure] Замечания по структуре каталогов Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
10502 Verilog Translator Bug New Normal subbytes.v line 76:13 no viable alternative at input '[' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9310 Retrascope Task Closed Normal substitute SMT-LIB variables those names are equal to builtin commands Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9227 Retrascope Feature Closed High support for 'BVEXTRACT(x y (SELECT z w))' constructions in left hand sides of assigments Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9039 Retrascope Feature Closed Normal Support for designs that assign to variable more than once Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
7723 Retrascope Task Rejected Normal Support for module instances in Verilog descriptions Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
6892 Retrascope Bug Closed Normal support for non-zero starting bitvectors Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7524 Verilog Translator Task Closed Normal support for non-zero-starting bit vector variables & signals Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5569 Retrascope Task Closed Normal support process variable declarations Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
10060 Retrascope Feature Resolved High Support SVA properties in CFG model Sergey Smolov Sergey Smolov Retrascope - 1.2 Actions
10202 Verilog Translator Bug Closed Normal SVA grammar warnings via assembling Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
10290 Verilog Translator Feature New Normal SystemVerilog support Sergey Smolov Actions
9936 Verilog Translator Bug Closed High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9288 QEMU4V Bug Closed Immediate /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’ Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
7730 MicroTESK Bug Closed High [tarmac-logger] missing "<cpu>" tag Sergey Smolov Andrei Tatarnikov MicroTESK - 2.4 Actions
10121 MicroTESK Bug Open Normal technical output printing at 'compile.sh' script running with '--help' option Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
8848 Verilog Translator Bug Closed Normal test_07_08_00_1.v: Module 'pullup' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8847 Verilog Translator Bug Closed Normal test_17_01_01_2_1.v: Module 'pulldown' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8846 Verilog Translator Bug Closed Normal test_19_04_00_3.v: Module 'real_last' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
6449 Retrascope Task New Low testbench generator taking test sequences and mappings as inputs Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
5145 Retrascope Task Closed Normal [testbench] Iface Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5443 Retrascope Bug Closed Normal [test][engine][media] TestVhdlTestbenchPrinterTestCase -> java.lang.RuntimeException: The exception has occurred while printing test pattern file Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5709 Retrascope Bug Closed Normal TestMinimiser.java:43: warning - @param argument "test" is not a parameter name. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
10287 Retrascope Feature Verified Normal TestModel: keep top level module name & variables Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9564 Retrascope Test Suite Task Closed Normal tests for EBMC tool Sergey Smolov Sergey Smolov Actions
9565 Retrascope Test Suite Task Closed Normal tests for Verilog2SMV tool Sergey Smolov Sergey Smolov Actions
9566 Retrascope Test Suite Task Closed Normal tests for Yosys-SMTBMC tool Sergey Smolov Sergey Smolov Actions
5827 Retrascope Bug Closed Normal TestVhdlTestbenchPrinterDummyTestCase -> NoSuchFileException Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5828 Retrascope Bug Closed Normal TestVhdlTestbenchPrinterVhdlTestCase -> IllegalArgumentException: Unexpected event value: true Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
6280 Retrascope Bug Closed Normal TestVhdlTestbenchPrinterVhdlTestCase: The exception has occurred while printing test pattern file Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5433 Fortress Task Closed Normal [test] write executable SMT-LIB code at testcase comments Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
6279 Retrascope Bug Closed Normal TestXmlPrinterTestCase: IllegalArgumentException: Output file name isn't specified Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9010 Retrascope Test Suite Bug Closed Normal Texas97CacheCoherenceVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Actions
9055 Verilog Translator Bug Closed High Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9011 Retrascope Test Suite Bug Closed Normal Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Sergey Smolov Actions
9172 Retrascope Test Suite Bug Closed Normal Texas97ParsepackCfgGraphMlTestCase: ru.ispras.retrascope.basis.exception.RetrascopeException: Wrong range: 0 < 0 or 7 > 1. Sergey Smolov Sergey Smolov Actions
9175 Retrascope Test Suite Bug Closed Normal Texas97PdlxCfgGraphMlTestCase: NullPointerException Sergey Smolov Sergey Smolov Actions
9334 QEMU4V Bug Closed Normal timestamp reset at MIPS trace Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
5251 Retrascope IDE Task New Normal [tool][configurator] Сохранение конфигураций Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
5702 Retrascope IDE Task New Normal [tool] create Retrascope icon Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
10081 Retrascope Bug Resolved High tool hangs right after final "Duration: " msg Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
6423 Fortress Task Rejected Low to_real, to_int, is_int operations Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
8869 QEMU4V Feature Closed Normal trace generation for Aarch64 programs Sergey Smolov Sergey Smolov Actions
8866 QEMU4V Feature Closed Normal trace generation for MIPS programs Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
8867 QEMU4V Feature Closed Normal trace generation for PowerPC (32bit) programs Sergey Smolov Maxim Chudnov QEMU4V - 0.3 Actions
8870 QEMU4V Feature Closed Normal trace generation for RISC-V programs Sergey Smolov Sergey Smolov Actions
7846 Fortress Task Rejected Normal 'Transformer.reduce(Transformer.substitute(expression, name, term))' convenience method Sergey Smolov Fortress - 0.4 Actions
5600 Fortress Task Closed High [transformer][ruleset] implement ITE rules Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
5424 Fortress Task Closed High [transformer][ruleset] дополнительные правила стандартизации Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
5419 Fortress Task Closed High [transformer][ruleset] реализовать правило expr==false -> NOT(expr == true) Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
5447 Fortress Task Closed High [transformer][ruleset] стандартизация константных выражений вида "x EQ y" Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
6352 Fortress Bug Closed High Transformer.standardize returns 'false' on (AND (EQ a 00) (NOT(EQ a b 00))) Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
5229 Fortress Task Closed High [transformer] Упрощение выражений с LOGIC_BOOLEAN Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
5651 Verilog Translator Task Closed Normal Translate logic operation results into Boolean expressions Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5704 Retrascope Task Closed Normal try to find a way to remove 'toplevel' option Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9776 Retrascope IDE Task Verified Normal try to use SVEditor instead of veditor Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9311 Verilog Translator Task Closed High type casting of expression operands Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7772 Fortress Task Closed High TypeConversion.coerce: transform from MAP to BIT_VECTOR Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
7555 Fortress Bug Closed Normal unable to create constraint-related jUnit tests including unused variables Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
9333 QEMU4V Bug Closed Normal unexpected hex value in MIPS trace Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9815 Retrascope IDE Task New Normal uninstaller for Retrascope IDE Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
6301 Retrascope Task Closed Normal unused code Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9278 Retrascope Task Closed Normal use CGAA model instead of EFSM-based assertions to get clocks Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
10133 Retrascope Task New Normal use '-coi' model checker option Sergey Smolov Mikhail Lebedev Retrascope - 1.1 Actions
10492 Fortress Task Closed Normal use CVC4 1.8 in testing Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
8288 Retrascope Task Closed Normal use DFS_NO_RPT walking where it is possible Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
9863 QEMU4V Task Closed Normal use Gradle 4.10.3 Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
10016 Trace Matcher Task Closed Normal Use Gradle 4.10.3 in build system Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
9291 Retrascope Task Closed Normal use nuXmv 1.1.1 Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
10058 Retrascope Task New Normal User documentation Sergey Smolov Sergey Smolov Retrascope - 1.2 Actions
9217 MicroTESK Task Closed Normal Use 'ru.ispras.castle.codegen' package classes from Castle Sergey Smolov Actions
9191 Retrascope Task Closed Normal use StringTemplate facilities to generate HDL testbenches Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
6990 Retrascope IDE Task Rejected Normal use veditor 1.2.1c Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
5755 Retrascope Task Closed Low use Zamia IG visitors & walkers Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5003 Retrascope Bug Rejected Normal [util] XmlUtilTest.java: java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5005 Retrascope Bug Closed Normal [util] XmlUtilTest: java.lang.AssertionError Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5420 Retrascope Task Closed Normal [util] метод fillNodeWithValues заменить на Transformer.substituteAllBindings Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
8831 Verilog Translator Bug Closed Normal vcegar-benchmarks/ipbdp/ipbdp_hier.v: java.lang.IllegalArgumentException: Bit vector sizes do not match: 4 != 32. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8990 Verilog Translator Bug Closed High vcegar-benchmarks/pi_bus/main_1.v: incorrect translation of nested "if" conditions Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9176 Retrascope Test Suite Bug Closed Normal VcegarHlddSmvPrinterTestCase: java.lang.IllegalArgumentException: Unknown operation 'BVSDIV' Sergey Smolov Mikhail Lebedev Actions
9296 Verilog Translator Bug Closed High vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8849 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_04_10_01_1 [floating point parameters]: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8850 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_1: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8851 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_3: java.lang.IllegalArgumentException: 0 must be > 0 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8852 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_4: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8853 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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