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# Project Tracker Status Priority Subject Author Assignee Target version
6989 Retrascope IDE Task Rejected Normal migrate to Eclipse Mars (4.5) Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
6988 Retrascope IDE Task New Normal [efsm][visualizator][zest] "organic" layout for EFSM models Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
6984 Retrascope IDE Bug Closed Normal java.io.IOException: Unable to resolve plug-in "platform:/plugin/retrascope-ide/icons/retrascope.gif". Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
6983 Retrascope IDE Task Closed Normal [cfg][visualizator][zest] visualize CfgAssertStatement & CfgLoopStatement nodes Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
6959 Retrascope IDE Bug Closed High java.lang.NullPointerException at startup Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
5702 Retrascope IDE Task New Normal [tool] create Retrascope icon Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
5547 Retrascope IDE Bug New Normal save Retrascope result not to ECLIPSE_HOME folder Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
5546 Retrascope IDE Task New Normal [log] print Retrascope log to Eclipse log Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
5251 Retrascope IDE Task New Normal [tool][configurator] Сохранение конфигураций Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
5127 Retrascope IDE Task Rejected Normal [cfg][printer][graphml] Интегрировать плагин для yEd Sergey Smolov Alexander Protsenko Actions
4991 Retrascope IDE Bug Closed Normal Не передается путь к HDL-описанию Sergey Smolov Alexander Kamkin Actions
9482 Retrascope RISC-V Benchmark Bug Closed Normal ru.ispras.retrascope.sample.VexRiscvVexRiscvGaddTestCase: ERROR: Wrong number of out edges for 'ru.ispras.retrascope.model.cfg.CfgBlockStatement@c219bf5': 2 Sergey Smolov Sergey Smolov Actions
9478 Retrascope RISC-V Benchmark Bug New Normal ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int' Sergey Smolov Actions
9477 Retrascope RISC-V Benchmark Bug New Normal an "import "DPI-C" function" construction causes Verilog Translator error Sergey Smolov Alexander Kamkin Actions
9475 Retrascope RISC-V Benchmark Bug Closed Normal Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '(' Sergey Smolov Alexander Kamkin Actions
9901 Retrascope Test Suite Bug New Low initializationError in some tests after Jenkins update Sergey Smolov Mikhail Lebedev Actions
9844 Retrascope Test Suite Bug Rejected Normal Bash scripts that run side tools (EBMC, SymbiYosys, Verilog2SMV) can't extract names of several Verilog modules Sergey Smolov Sergey Smolov Actions
9839 Retrascope Test Suite Task Rejected Normal scripts for commercial FV tools running Sergey Smolov Sergey Smolov Actions
9763 Retrascope Test Suite Bug Closed Normal missing javadoc headers in Java files of 'ru.ispras.retrascope.engine.hldd.printer.smv.spec.sample.vcegar' package Sergey Smolov Mikhail Lebedev Actions
9726 Retrascope Test Suite Task Closed Normal VerilogPrinter test cases Sergey Smolov Sergey Smolov Actions
9670 Retrascope Test Suite Task New High add 'ar.v' module to the test suite when SVA support will be implemented Sergey Smolov Sergey Smolov Actions
9607 Retrascope Test Suite Task Closed Normal add QUIP 9.0 benchmark Sergey Smolov Sergey Smolov Actions
9606 Retrascope Test Suite Task Closed Normal add IWLS 2005 benchmark Sergey Smolov Sergey Smolov Actions
9566 Retrascope Test Suite Task Closed Normal tests for Yosys-SMTBMC tool Sergey Smolov Sergey Smolov Actions
9565 Retrascope Test Suite Task Closed Normal tests for Verilog2SMV tool Sergey Smolov Sergey Smolov Actions
9564 Retrascope Test Suite Task Closed Normal tests for EBMC tool Sergey Smolov Sergey Smolov Actions
9309 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.engine.smv.testbench.sample.vcegar.VcegarPiBusAssertSmvTestbenchTestCase:line 2 column 34: invalid declaration, builtin symbol select Sergey Smolov Sergey Smolov Actions
9235 Retrascope Test Suite Task Closed Normal adapt JUnit components to new interface of ToolTest class Sergey Smolov Mikhail Lebedev Actions
9216 Retrascope Test Suite Task Closed Normal remove tests for Verilog Translator from project Sergey Smolov Mikhail Lebedev Actions
9203 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.basis.HlddAssertSmvTestbenchBenchmarkTest.runTest: java.lang.IllegalArgumentException: 'benchmarks' field is not initialized. Sergey Smolov Mikhail Lebedev Actions
9176 Retrascope Test Suite Bug Closed Normal VcegarHlddSmvPrinterTestCase: java.lang.IllegalArgumentException: Unknown operation 'BVSDIV' Sergey Smolov Mikhail Lebedev Actions
9175 Retrascope Test Suite Bug Closed Normal Texas97PdlxCfgGraphMlTestCase: NullPointerException Sergey Smolov Sergey Smolov Actions
9172 Retrascope Test Suite Bug Closed Normal Texas97ParsepackCfgGraphMlTestCase: ru.ispras.retrascope.basis.exception.RetrascopeException: Wrong range: 0 < 0 or 7 > 1. Sergey Smolov Sergey Smolov Actions
9071 Retrascope Test Suite Bug Open Normal ru.ispras.retrascope.engine.hldd.printer.smv.Texas97HlddSmvPrinterTestCase.runTest: java.lang.IllegalArgumentException: Unknown operation 'FUNCTION' Sergey Smolov Mikhail Lebedev Actions
9012 Retrascope Test Suite Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
9011 Retrascope Test Suite Bug Closed Normal Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Sergey Smolov Actions
9010 Retrascope Test Suite Bug Closed Normal Texas97CacheCoherenceVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Actions
4674 TestBase Task New Normal Тестовые ситуации Sergey Smolov Artem Kotsynyak TestBase - 0.0 Actions
10100 Trace Matcher Feature Resolved Normal "--boot-size <num>" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10099 Trace Matcher Feature Resolved Normal "--start-addr <hex value>" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10018 Trace Matcher Task Closed Normal migrate to Python 3 Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10017 Trace Matcher Task Closed Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10016 Trace Matcher Task Closed Normal Use Gradle 4.10.3 in build system Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10015 Trace Matcher Feature Closed Normal Report an error when input file is empty Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8433 Trace Matcher Feature Closed Normal "--skip-equal" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8432 Trace Matcher Task Closed Normal register records: register names can contain all but space symbols Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8242 Trace Matcher Bug Closed Normal print hexadecimal values to the output file in the same form as they were at input flies Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8206 Trace Matcher Feature Closed Normal "--debug" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8199 Trace Matcher Feature Closed Normal "ignore-the-rest" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8198 Trace Matcher Feature Closed Normal "exit-on-first-divergence" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8197 Trace Matcher Feature Closed Normal "matching window in ticks" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8184 Trace Matcher Task Closed Normal compare record fields in case insensitive mode Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8181 Trace Matcher Task Closed Normal check whether trace records are ordered by time Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8179 Trace Matcher Task Closed Normal ChangeLog Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8161 Trace Matcher Task Closed Normal Basic modules Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8113 Trace Matcher Task Closed Normal Gradle build environment Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
7733 Trace Matcher Task Closed Normal run.bat script for Windows Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
7732 Trace Matcher Task Closed Normal oracle: record queue based comparison approach Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
7663 Trace Matcher Task Closed Normal "main" function Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10513 Verilog Translator Bug New Normal macOS related line endings at Verilog modules Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10512 Verilog Translator Bug New Normal ADDA162H90A_atop.v line 120:47 mismatched input ':' expecting RPAREN Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10510 Verilog Translator Bug New Normal ERROR: [Internal] Bit vector sizes do not match: 32 != 2. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10509 Verilog Translator Bug New Normal ERROR: [Internal] 0 must be > 0 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10508 Verilog Translator Bug New Normal ERROR: [Internal] Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10505 Verilog Translator Bug New Normal ERROR: [Internal] 11 must be within range [0, 1) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10502 Verilog Translator Bug New Normal subbytes.v line 76:13 no viable alternative at input '[' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10382 Verilog Translator Bug Closed Normal java.lang.IllegalArgumentException: expression=(BVREPEAT test.uut._saxi_maskwidth 1) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10290 Verilog Translator Feature New Normal SystemVerilog support Sergey Smolov Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10245 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_pci_wbw_wbr_fifos: ERROR: [Internal] null Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10241 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_dctub_jpeg: ERROR: ..\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 1:70 mismatched character '\r' expecting '\n' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10237 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10216 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10215 Verilog Translator Bug New Normal ERROR: Starting points limit has been exhausted: 2255 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10202 Verilog Translator Bug Closed Normal SVA grammar warnings via assembling Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
10173 Verilog Translator Bug Closed High javadoc: DefineStructure.java:37: warning: no @return Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10141 Verilog Translator Bug Closed Normal check port redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10131 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10009 Verilog Translator Task Closed Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9993 Verilog Translator Bug New High if two modules are passed to the tool and one includes another, the tool hangs Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9990 Verilog Translator Feature Closed High check for variable/net redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9962 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Closed High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9915 Verilog Translator Bug Closed Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9904 Verilog Translator Task Closed Normal add info for "--library-file" cmdline option Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for '<var name>' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9899 Verilog Translator Task Closed Normal VerilogPrinter test cases for QUIP benchmarks Sergey Smolov Maxim Chudnov Verilog Translator - 0.1 Actions
9859 Verilog Translator Task New Normal modify "ERROR: [Internal] null" line at error log Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9848 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9822 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9811 Verilog Translator Task Closed High macro with parameters Sergey Smolov Alexey Danilov Verilog Translator - 0.2 Actions
9803 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.MulFifoTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator$1.getNode(VerilogElaborator.java:932) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9784 Verilog Translator Bug Closed Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9775 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9771 Verilog Translator Task Closed Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
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