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# Project Tracker Status Priority Subject Author Assignee Target version
10031 MicroTESK for PowerPC Bug New Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for PowerPC - 0.0 Actions
9374 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.BoundaryTestCase: Simulation failedThe CPR storage is not defined in the model.ru.ispras.microtesk.model.ConfigurationException: The CPR storage is not defined in the model. Sergey Smolov Alexander Protsenko Actions
9892 MicroTESK for RISC-V Bug Closed Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for RISC-V - 0.1 Actions
9375 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.GroupTestCase: org.jruby.exceptions.RaiseException: (NoMethodError) undefined method `la' for #<GroupGenTemplate:0x6046f0da> Sergey Smolov Alexander Protsenko Actions
6354 Retrascope Task Closed Normal Collapsing group node for Module Sergey Smolov Alexander Protsenko Retrascope - 0.1 Actions
9915 Verilog Translator Bug Verified Urgent "Cycle inclusion has been detected in fine <filename>" error is reported for Verilog modules that use the same another file Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10173 Verilog Translator Bug Verified High javadoc: DefineStructure.java:37: warning: no @return Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Verified High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10237 Verilog Translator Bug Verified High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9811 Verilog Translator Task Verified High macro with parameters Sergey Smolov Alexey Danilov Verilog Translator - 0.2 Actions
10216 Verilog Translator Bug Verified High ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9990 Verilog Translator Feature Verified High check for variable/net redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9962 Verilog Translator Bug Verified High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10141 Verilog Translator Bug Verified Normal check port redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10245 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_pci_wbw_wbr_fifos: ERROR: [Internal] null Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
6394 Local Support Project Bug New Normal Проект HDL Retrascope: на 17-дюймовом мониторе не масштабируется таблица Задачи Sergey Smolov Alexey Demakov Actions
3565 Local Support Project Bug Closed Normal Перестали приходить уведомления на почту об изменениях в проектах Sergey Smolov Alexey Demakov Actions
2494 CTESK Bug New Normal warning at build log Sergey Smolov Alexey Demakov Actions
3528 Local Support Project Bug Closed Normal Не отображается полный адрес svn-репозиториев Sergey Smolov Alexey Demakov Actions
5464 Fortress Task Closed High [solver] boolean expressions casting into bit vectors Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
5425 Fortress Bug Closed High [expression] java.lang.IllegalArgumentException: Expression is not a condition: (BVEXTRACT D_IN 0 0) Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
4813 Fortress Bug Closed High [solver][constraint] Невозможно создавать тривиальные ограничения Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
8665 Fortress Feature Closed High Nodes.BVEXTRACT(Node, Node, Node) convenience method Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
5985 Fortress Task Closed High Node ExprUtils.getEquation(Node target, Node value) Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
7730 MicroTESK Bug Closed High [tarmac-logger] missing "<cpu>" tag Sergey Smolov Andrei Tatarnikov MicroTESK - 2.4 Actions
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