Project

General

Profile

Issues

Filters

Apply Clear

# Project Tracker Status Priority Subject Author Assignee Target version
9363 QEMU4V Task Closed Normal remove 'set_q4v_tstamp' function calls from RISC-V/MIPS/Aarch64 'cpu_loop.c' modules Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
9216 Retrascope Test Suite Task Closed Normal remove tests for Verilog Translator from project Sergey Smolov Mikhail Lebedev Actions
9232 Verilog Translator Task Closed High remove typedefs from texas97-tests/PPC60X_bus/src/define.v Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9766 Retrascope Task Closed High remove 'vhdl.record' Git branch from remote repo Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
5887 Retrascope Task Closed Normal rename 'decider_parser.vhd' Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
10128 Retrascope Task Verified Normal rename multi-test classes: "*TestCase" -> "*TestSuite" Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
10166 Retrascope Task Resolved Normal rename some class fields & related methods Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10015 Trace Matcher Feature Closed Normal Report an error when input file is empty Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
5526 Retrascope Task Rejected Normal Retrascope engines configuration Sergey Smolov Alexander Kamkin Actions
8975 Retrascope Task Closed Normal RetrascopeException.makeException -> RetrascopeException.exception Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
5870 Retrascope Task Closed Normal Retrascope exceptions Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9816 Retrascope IDE Bug New Normal Retrascope IDE does not appear in "Installed Software" menu Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
5492 Verilog Translator Bug Closed Normal retrascope + sapic.v = java.lang.IllegalStateException: Operand is not a constant integer value: 00000000000000000000000000000011 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
6758 Retrascope Task Closed Normal return state/transition coverage for the specified EFSM & test entities Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
9427 Retrascope Task Closed Normal reuse variables' versions upon CGAA model building Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9806 Retrascope Task Closed Normal rm dependency from commons-lang library Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9889 MicroTESK for Plasma Task Resolved Normal rm deprecated 'findbugs' plugin from Gradle build script Sergey Smolov Actions
7423 Retrascope Bug Rejected High rnd_fsm.vhd: empty tst file Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
9436 MicroTESK Bug Closed Normal ru.ispras.microtesk.mmu.translator.GeneralTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
9437 MicroTESK Bug Closed Normal ru.ispras.microtesk.model.minimips.BufferPreparatorTestCase: QEMU4V crashes with general protection error on this test program Sergey Smolov Sergey Smolov MicroTESK - 2.4 Actions
9374 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.BoundaryTestCase: Simulation failedThe CPR storage is not defined in the model.ru.ispras.microtesk.model.ConfigurationException: The CPR storage is not defined in the model. Sergey Smolov Alexander Protsenko Actions
9375 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.GroupTestCase: org.jruby.exceptions.RaiseException: (NoMethodError) undefined method `la' for #<GroupGenTemplate:0x6046f0da> Sergey Smolov Alexander Protsenko Actions
9386 MicroTESK for PowerPC Bug Closed High ru.ispras.microtesk.model.powerpc.InstructionALUTestCase: Assembler messages: ../microtesk-powerpc/build/test/instruction_alu/instruction_alu_0000.s:1: Error: junk at end of line, first unrecognized character is `/' Sergey Smolov Sergey Smolov Actions
9387 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.InstructionBPUTestCase: ../microtesk-powerpc/build/test/instruction_bpu/instruction_bpu_0000.s:47: Error: operand out of range (0x0000000000002774 is not between 0x0000000000000000 and 0x000000000000001 Sergey Smolov Alexander Protsenko Actions
9203 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.basis.HlddAssertSmvTestbenchBenchmarkTest.runTest: java.lang.IllegalArgumentException: 'benchmarks' field is not initialized. Sergey Smolov Mikhail Lebedev Actions
3980 Retrascope Bug Closed Normal ru.ispras.retrascope.cfg.lib.examples.FIFOExample.java compilation error Sergey Smolov Sergey Smolov Actions
10266 Retrascope Bug Verified Normal ru.ispras.retrascope.engine.hldd.printer.smv.HlddSmvPrinterTestCase.runTest: java.lang.NullPointerException Sergey Smolov Mikhail Lebedev Retrascope - 1.1 Actions
10289 Retrascope Bug Verified Normal ru.ispras.retrascope.engine.hldd.printer.smv.property.HlddPropertySmvPrinterTestCase.runTest: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Mikhail Lebedev Retrascope - 1.1 Actions
9071 Retrascope Test Suite Bug Open Normal ru.ispras.retrascope.engine.hldd.printer.smv.Texas97HlddSmvPrinterTestCase.runTest: java.lang.IllegalArgumentException: Unknown operation 'FUNCTION' Sergey Smolov Mikhail Lebedev Actions
9066 Retrascope Bug Closed Normal ru.ispras.retrascope.engine.hldd.printer.smv.Texas97HlddSmvPrinterTestCase.runTest: java.lang.NullPointerException Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9562 Retrascope Bug Closed Normal ru.ispras.retrascope.engine.hldd.printer.smv.usedef.MemStageUseDefSmvPrinterTestCase: model checker crashes without errors in *.smvlog Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9309 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.engine.smv.testbench.sample.vcegar.VcegarPiBusAssertSmvTestbenchTestCase:line 2 column 34: invalid declaration, builtin symbol select Sergey Smolov Sergey Smolov Actions
5778 Retrascope Bug Closed Normal ru.ispras.retrascope.engine.testbench.TestVhdlTestbenchPrinterTestCase -> java.util.NoSuchElementException Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
10023 Retrascope Bug Verified High ru.ispras.retrascope.parser.verilog.VerilogParserTestCase: java.lang.Exception: Method runTest should have no parameters Sergey Smolov Maxim Chudnov Retrascope - 1.1 Actions
9482 Retrascope RISC-V Benchmark Bug Closed Normal ru.ispras.retrascope.sample.VexRiscvVexRiscvGaddTestCase: ERROR: Wrong number of out edges for 'ru.ispras.retrascope.model.cfg.CfgBlockStatement@c219bf5': 2 Sergey Smolov Sergey Smolov Actions
5871 Retrascope Bug Closed Normal ru.ispras.retrascope.test.printer.testbench -> ru.ispras.retrascope.engine.test.printer.testbench Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9282 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9190 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8786 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.FifoTestbenchTestCase fails Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9962 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9160 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9182 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.MulFifoTestCase: java.lang.IllegalStateException: Parameter is not a value: i Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9803 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.MulFifoTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator$1.getNode(VerilogElaborator.java:932) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9202 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.PjIcuIcctl1TestCase: java.lang.ArrayIndexOutOfBoundsException: 3 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9775 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9822 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10131 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10241 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_dctub_jpeg: ERROR: ..\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 1:70 mismatched character '\r' expecting '\n' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10216 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: java.lang.NullPointerException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10245 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_pci_wbw_wbr_fifos: ERROR: [Internal] null Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9225 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_MPEG_prefixcode: ERROR: ../texas97-tests/MPEG/prefixcode.v line 70:8 no viable alternative at input ';' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9224 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10237 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestSuite#runTest_Pi_Bus_single_master_main2: ERROR: Cycle inclusion at: '...bus.v' Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9223 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_pj_icu_icctl1: ERROR: Declaration of 'clk' has not been found Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9226 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9848 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9222 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9212 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7733 Trace Matcher Task Closed Normal run.bat script for Windows Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
5904 Retrascope Task Closed Normal save jUnit test results in build/test-results Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5547 Retrascope IDE Bug New Normal save Retrascope result not to ECLIPSE_HOME folder Sergey Smolov Maxim Chudnov Retrascope IDE - 0.1 Actions
9839 Retrascope Test Suite Task Rejected Normal scripts for commercial FV tools running Sergey Smolov Sergey Smolov Actions
9249 Retrascope Task Closed Normal separate jUnit test cases for EfsmGraphMlPrinter engine Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
8194 Retrascope Task Closed Normal Separately solve independent sub-expressions of common AND expression Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5399 Fortress Task Closed Normal silent & debug mode Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
6059 Retrascope Task Closed Normal Simple solver for "x && !x" constraints Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
3716 С++TESK Development Environment Task Closed Normal Simple XML dumping\parsing test Sergey Smolov asd ert Actions
8433 Trace Matcher Feature Closed Normal "--skip-equal" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
8304 Retrascope Feature Rejected Normal SLR values number limit Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
4713 Fortress Task New High SMT-LIB structures Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
10001 Fortress Task Rejected Normal SMT-LIBv2 benchmarks Sergey Smolov Actions
6447 Retrascope Task Closed Normal SMV-based counterexamples parser Sergey Smolov Mikhail Lebedev Retrascope - 0.2 Actions
7104 Retrascope Task Closed High smv-test-parser: filter tests Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5464 Fortress Task Closed High [solver] boolean expressions casting into bit vectors Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
4813 Fortress Bug Closed High [solver][constraint] Невозможно создавать тривиальные ограничения Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
4673 Fortress Task Closed Normal [solver][constraint] Ограничения без имен Sergey Smolov Sergey Smolov Fortress - 0.3 Actions
4802 Fortress Task Closed Normal [solver][constraint] создание Constraint без указания variables Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
5318 Fortress Task Closed Low [solver][expression] Реализовать метод разрешения ограничений SolverResult solve(Constraint constraint) Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
4797 Fortress Bug Closed Normal [solver] NullPointerException when solver is not found Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
5466 Fortress Task Closed High [solver] print the input constraint when solver returns ERROR/UNKNOWN verdict Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
5162 Fortress Bug Closed Normal [solver] ReductionCustomOperationsTestCase -> java.lang.AssertionError Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
6364 Fortress Task Rejected Low SolverResult: implement equals\hashcode methods Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
8204 Fortress Feature Closed Normal solver-specific header for generated SMT2 files Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
4554 Fortress Task Closed Normal [solver][xml] Метод преобразования ограничения в XML-based String Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
3654 С++TESK Development Environment Task Closed High source code refactoring Sergey Smolov Sergey Smolov Actions
6808 Retrascope Task Rejected High Split CFG processes into independent parts Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6362 Retrascope Bug Rejected Normal src/test/verilog/adder/adder4_testbench.v: wrong CFG model Sergey Smolov Mikhail Chupilko Retrascope - 0.1 Actions
6363 Verilog Translator Bug Closed High src/test/verilog/fifo0/mem_2p.v: AbstractMethodError Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
(401-500/688) Per page: 25, 50, 100

Also available in: Atom CSV PDF