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# Project Tracker Status Priority Subject Author Assignee Target version
8864 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_17_10_02_1_i: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10121 MicroTESK Bug Open Normal technical output printing at 'compile.sh' script running with '--help' option Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
4946 Retrascope Task Closed Normal [basis][log] Ведение лога для нескольких логгеров Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
4991 Retrascope IDE Bug Closed Normal Не передается путь к HDL-описанию Sergey Smolov Alexander Kamkin Actions
4945 Retrascope Task Closed Normal [basis][log] Опция логирования Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
10094 MicroTESK Bug Verified Normal strange common code at LinkerScript.stg Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
8858 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_01_2: java.lang.IllegalStateException: Parameter is not a value: (BVZEROEXT 2147483646 i) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10215 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000_lut: ERROR: Starting points limit has been exhausted: 2255 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10241 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_dctub_jpeg: ERROR: ..\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 1:70 mismatched character '\r' expecting '\n' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8851 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_3: java.lang.IllegalArgumentException: 0 must be > 0 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10131 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10074 MicroTESK Feature New Normal option that stores boot obj at the generated ld script Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
8854 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_02_2: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8681 Retrascope Bug Closed Normal EngineRegistry fails to create toolchain when HashSet\HashMap are used Sergey Smolov Alexander Kamkin Retrascope - 1.0 Actions
5526 Retrascope Task Rejected Normal Retrascope engines configuration Sergey Smolov Alexander Kamkin Actions
8849 Verilog Translator Bug Verified Normal VerilogIeeeTestCase.runTest_04_10_01_1 [floating point parameters]: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9376 MicroTESK for MIPS Bug New Normal Warning: Group MIPS64FpuOp contains two items add_fmt and mfc1 with the same opcode 01000100000000000000000000000000 Sergey Smolov Alexander Kamkin Actions
8853 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5455 Verilog Translator Task Closed Normal устранить зависимость от ANTLRWorks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9375 MicroTESK for PowerPC Bug Closed Normal ru.ispras.microtesk.model.powerpc.autogen.GroupTestCase: org.jruby.exceptions.RaiseException: (NoMethodError) undefined method `la' for #<GroupGenTemplate:0x6046f0da> Sergey Smolov Alexander Protsenko Actions
9892 MicroTESK for RISC-V Bug Closed Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for RISC-V - 0.1 Actions
10031 MicroTESK for PowerPC Bug New Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for PowerPC - 0.0 Actions
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