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# Project Tracker Status Priority Subject Author Assignee Target version
9174 Verilog Translator Bug Closed High NullPointerException via VerilogLiteral construction Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8990 Verilog Translator Bug Closed High vcegar-benchmarks/pi_bus/main_1.v: incorrect translation of nested "if" conditions Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9239 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5608 Retrascope Bug Closed High [efsm][generator][test][fate] FATE generator hangs at b03 description from ITC'99 Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9250 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.IfStageTestCase: src/test/verilog/rest-tests/mips16/IF_stage.v line 31:9 missing KW_BEGIN at 'pc' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9055 Verilog Translator Bug Closed High Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5510 Retrascope Bug Closed High [efsm][generator][test] RandomFateSequenceIterator compilation error Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5715 Retrascope Bug Closed High EfsmTestGenerator.java:138: error: method put in interface Map<K,V> cannot be applied to given types -> traversedPaths.put(efsm, new HashSet<>()); Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5528 Retrascope Bug Closed High [engine][testbench] java.nio.file.FileAlreadyExistsException: decider_parser.vhd Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9160 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5873 Retrascope Bug Closed High missing transitions in b04 EFSM Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9212 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5425 Fortress Bug Closed High [expression] java.lang.IllegalArgumentException: Expression is not a condition: (BVEXTRACT D_IN 0 0) Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
4813 Fortress Bug Closed High [solver][constraint] Невозможно создавать тривиальные ограничения Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
9165 Verilog Translator Bug Closed High Incorrect parameter value calculation at hierarchical Verilog description Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9386 MicroTESK for PowerPC Bug Closed High ru.ispras.microtesk.model.powerpc.InstructionALUTestCase: Assembler messages: ../microtesk-powerpc/build/test/instruction_alu/instruction_alu_0000.s:1: Error: junk at end of line, first unrecognized character is `/' Sergey Smolov Sergey Smolov Actions
6263 Retrascope Bug Closed High Crash when test generation engine elaborates EFSMs from alu.vhd: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6959 Retrascope IDE Bug Closed High java.lang.NullPointerException at startup Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
9224 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9209 Verilog Translator Bug Closed High java.util.EmptyStackException at ru.ispras.verilog.parser.util.TokenSourceStack.getLastParentToken(TokenSourceStack.java:70) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9222 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Sampleq_twoFifo1: java.lang.IllegalStateException: Parameter is not a value: LOGLENGTH Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5453 Fortress Bug Closed High [arrays] Unexpected solver output: " (INSTQUEUE ((as const (Array Int Int)) 0))" Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
6352 Fortress Bug Closed High Transformer.standardize returns 'false' on (AND (EQ a 00) (NOT(EQ a b 00))) Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
5461 Fortress Bug Closed High [arrays] Insufficient arrays support Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
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