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# Project Tracker Status Priority Subject Author Assignee Target version
9993 Verilog Translator Bug New High if two modules are passed to the tool and one includes another, the tool hangs Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10131 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8857 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_02_02_2_1: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9904 Verilog Translator Task Verified Normal add info for "--library-file" cmdline option Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9859 Verilog Translator Task New Normal modify "ERROR: [Internal] null" line at error log Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8849 Verilog Translator Bug Verified Normal VerilogIeeeTestCase.runTest_04_10_01_1 [floating point parameters]: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9775 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8831 Verilog Translator Bug Closed Normal vcegar-benchmarks/ipbdp/ipbdp_hier.v: java.lang.IllegalArgumentException: Bit vector sizes do not match: 4 != 32. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8854 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_02_2: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7725 Verilog Translator Task Closed Normal bitvector arrays support Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9165 Verilog Translator Bug Closed High Incorrect parameter value calculation at hierarchical Verilog description Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9182 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.MulFifoTestCase: java.lang.IllegalStateException: Parameter is not a value: i Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9282 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DataMemTestCase: DEBUG: Reduce: (BVEXTRACT 0 7 mem_access_addr) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8864 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_17_10_02_1_i: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5249 Retrascope Task Closed High [basis] Настройка Retrascope для работы с SMT-решателями Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
5247 Retrascope Task Closed Normal [basis] Набор идентификаторов Engine как опция командной строки Retrascope Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
5258 Retrascope Task Closed High [basis] Обработка циклических зависимостей разных Engine Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
4945 Retrascope Task Closed Normal [basis][log] Опция логирования Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
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