Project

General

Profile

Issues

Filters

Apply Clear

# Project Tracker Status Priority Subject Author Assignee Target version
9333 QEMU4V Bug Closed Normal unexpected hex value in MIPS trace Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
8865 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_19_11_00_1: java.lang.IllegalArgumentException: Declaration=DECLARATION(), parent=MODULE(m2) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
6413 Retrascope Bug Closed Normal b03.vhd: different EFSM extraction stats Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
8573 Fortress Bug Closed Normal missing javadoc Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
6504 Retrascope Bug Closed Normal fifo/fifo.v: nuSMV model checker returns ERROR Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
3590 C++TESK Testing ToolKit Bug Closed Normal C++TesK installation fails on OpenSUSE 12.2 x64 Sergey Smolov Sergey Smolov C++TESK Testing ToolKit - 1.0 Actions
8242 Trace Matcher Bug Closed Normal print hexadecimal values to the output file in the same form as they were at input flies Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10041 QEMU4V Bug Closed Normal wrong names for PowerPC registers in trace Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
7555 Fortress Bug Closed Normal unable to create constraint-related jUnit tests including unused variables Sergey Smolov Artem Kotsynyak Fortress - 0.4 Actions
9309 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.engine.smv.testbench.sample.vcegar.VcegarPiBusAssertSmvTestbenchTestCase:line 2 column 34: invalid declaration, builtin symbol select Sergey Smolov Sergey Smolov Actions
6425 Retrascope Bug Closed Normal b12.vhd: XmvExprPrinter.getConstant(XmvExprPrinter.java:330) -> NullPointerException Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
5443 Retrascope Bug Closed Normal [test][engine][media] TestVhdlTestbenchPrinterTestCase -> java.lang.RuntimeException: The exception has occurred while printing test pattern file Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
6424 Retrascope Bug Closed Normal b05.vhd: line 64: at token "d32_-10": syntax error Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
5871 Retrascope Bug Closed Normal ru.ispras.retrascope.test.printer.testbench -> ru.ispras.retrascope.engine.test.printer.testbench Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
8289 Retrascope Bug Closed Normal ITC99 b02: no resetting transition has been found Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8847 Verilog Translator Bug Closed Normal test_17_01_01_2_1.v: Module 'pulldown' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9203 Retrascope Test Suite Bug Closed Normal ru.ispras.retrascope.basis.HlddAssertSmvTestbenchBenchmarkTest.runTest: java.lang.IllegalArgumentException: 'benchmarks' field is not initialized. Sergey Smolov Mikhail Lebedev Actions
5828 Retrascope Bug Closed Normal TestVhdlTestbenchPrinterVhdlTestCase -> IllegalArgumentException: Unexpected event value: true Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
6279 Retrascope Bug Closed Normal TestXmlPrinterTestCase: IllegalArgumentException: Output file name isn't specified Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9011 Retrascope Test Suite Bug Closed Normal Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Sergey Smolov Actions
8245 Retrascope Bug Closed Normal cfg-rnd-testgen: IllegalArgumentException at minimips\pps_pf.v Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
9010 Retrascope Test Suite Bug Closed Normal Texas97CacheCoherenceVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Actions
9784 Verilog Translator Bug Closed Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
6365 Retrascope Bug Closed Normal src/test/vhdl/example/example.vhd: IllegalArgumentException Sergey Smolov Mikhail Lebedev Retrascope - 0.1 Actions
8237 Retrascope Bug Closed Normal CFG random test generator works too slow on b19 Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8283 Retrascope Bug Closed Normal "X <= (others => '0')" should be translated properly when X is bit vector Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8285 Retrascope Bug Closed Normal 0% coverage of EFSM transitions for b01 example Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7720 Retrascope Bug Closed Normal mips16/data_mem.v: The expression to be computed (ram) contains unevaluated variables: [ram] Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5385 Java SoftFloat Bug Closed Normal Странная структура директорий проекта Sergey Smolov Alexander Kamkin Actions
5506 Retrascope Bug Closed Normal [javadoc] warning while EfsmAtomicFateTestGenerator processing Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
7593 Retrascope Bug Closed Normal mips16\data_mem.v: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7098 Verilog Translator Bug Closed Normal src/test/verilog/mips16/data_mem.v: 'mem_access_addr' has null declaration Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7576 Retrascope Bug Closed Normal mips16/hazard_detection_unit.v: java.lang.IllegalArgumentException: Constraint contains errors Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
3717 С++TESK Development Environment Bug Closed Normal Переименовать com.unitesk.cpptesk.ide.prototype.presentations в com.unitesk.cpptesk.ide.prototype.ir Sergey Smolov Sergey Smolov Actions
9365 QEMU4V Bug Closed Normal missing insn binary images in MIPS trace Sergey Smolov Sergey Smolov QEMU4V - 0.2 Actions
8738 Verilog Translator Bug Closed Normal DataMemTestCase falls with error Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5831 Retrascope Bug Closed Normal EfsmSimulator.java -> Tag @see: can't find getResetGuardedAction() in ru.ispras.retrascope.model.efsm.Efsm Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
7883 Retrascope Bug Closed Normal fifo_testbench.v: java.lang.NullPointerException Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
9066 Retrascope Bug Closed Normal ru.ispras.retrascope.engine.hldd.printer.smv.Texas97HlddSmvPrinterTestCase.runTest: java.lang.NullPointerException Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
6353 Retrascope Bug Closed Normal Case children of one Switch node can have equal NodeValue Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5538 Retrascope Bug Closed Normal [efsm][generator][test] EfsmFateTestGeneratorVhdlTestCase -> java.lang.RuntimeException: Unexpected simulation result. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5540 Retrascope Bug Closed Normal [javadoc] EfsmSimulator.java:119: warning - @param argument "efsm" is not a parameter name. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
7753 Retrascope Bug Closed Normal example.vhd: cannot generate SMV-based test Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5263 Retrascope Bug Rejected High [efsm][generator][test] EfsmTestGeneratorTestCase -> java.lang.OutOfMemoryError: Java heap space Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7423 Retrascope Bug Rejected High rnd_fsm.vhd: empty tst file Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
5648 Retrascope Bug Rejected High EfsmSimulator.executeAssignment -> Unsupported data type of ranged variable: (MAP LOGIC_INTEGER LOGIC_INTEGER) Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9844 Retrascope Test Suite Bug Rejected Normal Bash scripts that run side tools (EBMC, SymbiYosys, Verilog2SMV) can't extract names of several Verilog modules Sergey Smolov Sergey Smolov Actions
4005 C++TESK Testing ToolKit Bug Rejected Normal удалить пустой README Sergey Smolov asd ert C++TESK Testing ToolKit - 1.0 Actions
10236 Retrascope Bug Rejected Normal efsm-test-generator hangs at opencores/mips16/data_mem.v Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
5004 Retrascope Bug Rejected Normal [efsm][simulator][execution] ReferenceEfsmTestGeneratorTest.java : java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5003 Retrascope Bug Rejected Normal [util] XmlUtilTest.java: java.lang.RuntimeException: An error occured while trying to resolve a constraint. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
4928 Retrascope Bug Rejected Normal [cfg] Range может состоять из нескольких участков Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6366 Retrascope Bug Rejected Normal src/test/vhdl/example/test.vhd: Efsm.UNINITIALISED_STATE isn't supported yet Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
3605 Retrascope Bug Rejected Normal [vhdl][parser][cfg] Zamia не обрабатывает пакеты функций Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
7594 Retrascope Bug Rejected Normal ModelSim shows error when TST file contains multiple comments Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5692 Retrascope Bug Rejected Normal FATE/FATE+ hangs on b03 with Java 1.8 Sergey Smolov Igor Melnichenko Actions
6362 Retrascope Bug Rejected Normal src/test/verilog/adder/adder4_testbench.v: wrong CFG model Sergey Smolov Mikhail Chupilko Retrascope - 0.1 Actions
5684 Retrascope Bug Rejected Low computeExpression -> LOGIC_BOOLEAN vs (MAP LOGIC_INTEGER LOGIC_BOOLEAN) Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
10290 Verilog Translator Feature New Normal SystemVerilog support Sergey Smolov Actions
8587 MicroTESK Feature New Normal ISA subsets Sergey Smolov Artem Kotsynyak MicroTESK - 2.5 Actions
10074 MicroTESK Feature New Normal option that stores boot obj at the generated ld script Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
10088 QEMU4V Feature New Low QEMU4V formatted traces for x86 programs Sergey Smolov Actions
9247 Retrascope Feature Open High CFG-to-C printer Sergey Smolov Sergey Smolov Retrascope - 1.2 Actions
10060 Retrascope Feature Resolved High Support SVA properties in CFG model Sergey Smolov Sergey Smolov Retrascope - 1.2 Actions
10112 Retrascope Feature Resolved Normal '--no-phase' command line option for 'cfg-gadd-transformer' engine Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10125 Retrascope Feature Resolved Normal '--detailed' option for efsm-graphml-printer engine Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10238 Retrascope Feature Resolved Normal VerilogParser: '--library-file' cmdline option Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10116 Retrascope Feature Resolved Normal command line option to check if solvers\model checkers that are used are installed properly Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10099 Trace Matcher Feature Resolved Normal "--start-addr <hex value>" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
10100 Trace Matcher Feature Resolved Normal "--boot-size <num>" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
9990 Verilog Translator Feature Verified High check for variable/net redeclarations Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
10115 Retrascope Feature Verified Normal '--version' command line option Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
10287 Retrascope Feature Verified Normal TestModel: keep top level module name & variables Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
8874 Verilog Translator Feature Closed High mapping from instance variables to their code entries Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9123 Fortress Feature Closed High calculate DataType for 'BVEXTRACT(i, i, x)' NodeOperation objects Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
9227 Retrascope Feature Closed High support for 'BVEXTRACT(x y (SELECT z w))' constructions in left hand sides of assigments Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
8665 Fortress Feature Closed High Nodes.BVEXTRACT(Node, Node, Node) convenience method Sergey Smolov Andrei Tatarnikov Fortress - 0.4 Actions
9041 Retrascope Feature Closed Normal when model checker returns an error, print it's log to the Retrascope output Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9039 Retrascope Feature Closed Normal Support for designs that assign to variable more than once Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
8220 Retrascope Feature Closed Normal BV_INC6 VHDL function support Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8260 Retrascope Feature Closed Normal VHDL record support (non-aggregate case) Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
8615 Retrascope Feature Closed Normal "--no-backends" command line option Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9503 Retrascope Feature Closed Normal when debug option is enabled, pass it to the model checker as well Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9335 Retrascope Feature Closed Normal cgaa-assert-extractor engine Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9486 Retrascope Feature Closed Normal HDL parser's init_process backend: calculate initial values if possible Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9474 Retrascope Feature Closed Normal enable\disable backend parameters for all the engines Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9468 Retrascope Feature Closed Normal HDL parser backend that removes 'initial' processes Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9457 Retrascope Feature Closed Normal one more auxiliary path in GADD model for terminal endings Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9446 Retrascope Feature Closed Normal Debug output file for engines and their backends Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9264 Retrascope Feature Closed Normal '--disable-backends' cmdline option for HDL parser engine Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9769 Retrascope Feature Closed Normal GraphML printers: make branch values italic Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
8870 QEMU4V Feature Closed Normal trace generation for RISC-V programs Sergey Smolov Sergey Smolov Actions
9281 Retrascope Feature Closed Normal cmdline option that specifies clock variable for CGAA model Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
(201-300/675) Per page: 25, 50, 100

Also available in: Atom CSV PDF