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# Project Tracker Status Priority Subject Author Assignee Target version
6449 Retrascope Task New Low testbench generator taking test sequences and mappings as inputs Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
4363 Retrascope Task New Low Критерий кластеризации входных сигналов, основанный на GA Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
4521 Retrascope Task New Low Входной класс для генератора тестовой последовательности Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
9670 Retrascope Test Suite Task New High add 'ar.v' module to the test suite when SVA support will be implemented Sergey Smolov Sergey Smolov Actions
9478 Retrascope RISC-V Benchmark Bug New Normal ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int' Sergey Smolov Actions
9184 Veritool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
10290 Verilog Translator Feature New Normal SystemVerilog support Sergey Smolov Actions
10088 QEMU4V Feature New Low QEMU4V formatted traces for x86 programs Sergey Smolov Actions
8167 QEMU4V Task New Low Program flow tracing Sergey Smolov Actions
3755 С++TESK Development Environment Task New Normal namespace name for test system prototypes Sergey Smolov Actions
3756 С++TESK Development Environment Task New Immediate Генерация C++ кода для модели сообщений Sergey Smolov Actions
9888 Retrascope IDE Task New Normal complete migration from Ant to Gradle build system Sergey Smolov Retrascope IDE - 0.1 Actions
3659 С++TESK Development Environment Task New Normal Соответствие полей классов сообщений и сигналов HDL-модели Sergey Smolov Actions
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