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# Project Tracker Status Priority Subject Author Assignee Target version
10088 QEMU4V Feature New Low QEMU4V formatted traces for x86 programs Sergey Smolov Actions
10001 Fortress Task Rejected Normal SMT-LIBv2 benchmarks Sergey Smolov Actions
9889 MicroTESK for Plasma Task Resolved Normal rm deprecated 'findbugs' plugin from Gradle build script Sergey Smolov Actions
9478 Retrascope RISC-V Benchmark Bug New Normal ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int' Sergey Smolov Actions
9217 MicroTESK Task Closed Normal Use 'ru.ispras.castle.codegen' package classes from Castle Sergey Smolov Actions
9184 Veritool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
9012 Retrascope Test Suite Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
8167 QEMU4V Task New Low Program flow tracing Sergey Smolov Actions
3759 С++TESK Development Environment Task Feedback Normal Разработать демонстрационный пример для структуры соответствия Sergey Smolov Actions
3756 С++TESK Development Environment Task New Immediate Генерация C++ кода для модели сообщений Sergey Smolov Actions
3755 С++TESK Development Environment Task New Normal namespace name for test system prototypes Sergey Smolov Actions
3659 С++TESK Development Environment Task New Normal Соответствие полей классов сообщений и сигналов HDL-модели Sergey Smolov Actions
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