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# Project Tracker Status Priority Subject Author Assignee Target version
6983 Retrascope IDE Task Closed Normal [cfg][visualizator][zest] visualize CfgAssertStatement & CfgLoopStatement nodes Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
6990 Retrascope IDE Task Rejected Normal use veditor 1.2.1c Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
9998 Castle Task Closed Normal README -> README.md Sergey Smolov Sergey Smolov Castle - 0.1 Actions
9999 Castle Task Closed Normal ChangeLog -> ChangeLog.md Sergey Smolov Sergey Smolov Castle - 0.1 Actions
6507 Castle Task Closed Normal build.gradle: get ANTLR jar from server Sergey Smolov Sergey Smolov Actions
9899 Verilog Translator Task Closed Normal VerilogPrinter test cases for QUIP benchmarks Sergey Smolov Maxim Chudnov Verilog Translator - 0.1 Actions
9904 Verilog Translator Task Closed Normal add info for "--library-file" cmdline option Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10009 Verilog Translator Task Closed Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9859 Verilog Translator Task New Normal modify "ERROR: [Internal] null" line at error log Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9771 Verilog Translator Task Closed Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9208 Verilog Translator Task Closed Normal add Verilog2Smv\VIS benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9207 Verilog Translator Task Closed Normal add VCEGAR benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9206 Verilog Translator Task Closed Normal add Texas97 benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7725 Verilog Translator Task Closed Normal bitvector arrays support Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8982 Verilog Translator Task New Normal "for" loop unrolling Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7524 Verilog Translator Task Closed Normal support for non-zero-starting bit vector variables & signals Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5881 Verilog Translator Task Closed Normal keep file names in the AST top nodes Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5651 Verilog Translator Task Closed Normal Translate logic operation results into Boolean expressions Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8205 Verilog Translator Task Closed Normal Gradle-based build environment Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5455 Verilog Translator Task Closed Normal устранить зависимость от ANTLRWorks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5755 Retrascope Task Closed Low use Zamia IG visitors & walkers Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4521 Retrascope Task New Low Входной класс для генератора тестовой последовательности Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
4363 Retrascope Task New Low Критерий кластеризации входных сигналов, основанный на GA Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
6449 Retrascope Task New Low testbench generator taking test sequences and mappings as inputs Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
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