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# Project Tracker Status Priority Subject Author Assignee Target version
8433 Trace Matcher Feature Closed Normal "--skip-equal" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
7527 Fortress Task Closed Normal constant casting while type conversion Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
8203 Fortress Feature Closed Normal bv2nat\int2bv operations Sergey Smolov Sergey Smolov Fortress - 0.4 Actions
4363 Retrascope Task New Low Критерий кластеризации входных сигналов, основанный на GA Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
6448 Retrascope Task New Low mapping description language + IR + parser Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
6449 Retrascope Task New Low testbench generator taking test sequences and mappings as inputs Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
5570 Retrascope Task Closed Low [build] build.xml: extract equal code parts from 'test'/'test.short' targets Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5548 Retrascope Task Closed Low elaborate minimips modules Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5755 Retrascope Task Closed Low use Zamia IG visitors & walkers Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4521 Retrascope Task New Low Входной класс для генератора тестовой последовательности Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
3756 С++TESK Development Environment Task New Immediate Генерация C++ кода для модели сообщений Sergey Smolov Actions
3659 С++TESK Development Environment Task New Normal Соответствие полей классов сообщений и сигналов HDL-модели Sergey Smolov Actions
9184 VeriTool Bug New Normal ERROR: Unable to read config file: /usr/lib/x86_64-linux-gnu/ivl/veritool.conf Sergey Smolov Actions
7846 Fortress Task Rejected Normal 'Transformer.reduce(Transformer.substitute(expression, name, term))' convenience method Sergey Smolov Fortress - 0.4 Actions
10001 Fortress Task Rejected Normal SMT-LIBv2 benchmarks Sergey Smolov Actions
10290 Verilog Translator Feature New Normal SystemVerilog support Sergey Smolov Actions
9012 Retrascope Test Suite Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
9888 Retrascope IDE Task New Normal complete migration from Ant to Gradle build system Sergey Smolov Retrascope IDE - 0.1 Actions
9217 MicroTESK Task Closed Normal Use 'ru.ispras.castle.codegen' package classes from Castle Sergey Smolov Actions
3759 С++TESK Development Environment Task Feedback Normal Разработать демонстрационный пример для структуры соответствия Sergey Smolov Actions
3755 С++TESK Development Environment Task New Normal namespace name for test system prototypes Sergey Smolov Actions
9889 MicroTESK for Plasma Task Resolved Normal rm deprecated 'findbugs' plugin from Gradle build script Sergey Smolov Actions
9478 Retrascope RISC-V Benchmark Bug New Normal ERROR: retrascope-riscv\src\main\verilog\rocket-chip\src\main\resources\vsrc\TestDriver.v line 28:2 no viable alternative at input 'int' Sergey Smolov Actions
10088 QEMU4V Feature New Low QEMU4V formatted traces for x86 programs Sergey Smolov Actions
8167 QEMU4V Task New Low Program flow tracing Sergey Smolov Actions
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