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# Project Tracker Status Priority Subject Author Assignee Target version
8865 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_19_11_00_1: java.lang.IllegalArgumentException: Declaration=DECLARATION(), parent=MODULE(m2) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8832 Verilog Translator Bug Closed Normal verilog/opencores/mips16/IF_stage.v: java.lang.IllegalStateException: Parameter is not a value: (BVSUB 8 1) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5578 Retrascope Task Closed Normal [verilog][parser][cfg] add support of multiple assignments Sergey Smolov Mikhail Chupilko Retrascope - 0.1 Actions
5404 Retrascope Bug Closed Normal [verilog][parser][cfg] java.lang.IllegalArgumentException: Unsupported data type: UNKNOWN Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
5398 Retrascope Task Closed Normal [verilog][parser][cfg] Преобразование констант в NodeValue Sergey Smolov Mikhail Chupilko Retrascope - 0.1 Actions
10238 Retrascope Feature Resolved Normal VerilogParser: '--library-file' cmdline option Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9726 Retrascope Test Suite Task Closed Normal VerilogPrinter test cases Sergey Smolov Sergey Smolov Actions
9899 Verilog Translator Task Verified Normal VerilogPrinter test cases for QUIP benchmarks Sergey Smolov Maxim Chudnov Verilog Translator - 0.1 Actions
5567 Verilog Translator Bug Closed High VerilogStaticChecker.ExpressionVisitor is not abstract and does not override abstract method getOperandOrder() in ExprTreeVisitor Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10115 Retrascope Feature Verified Normal '--version' command line option Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
5549 Retrascope Task Closed Normal [vhdl][cfg][parser] add support of instantiation Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
3605 Retrascope Bug Rejected Normal [vhdl][parser][cfg] Zamia не обрабатывает пакеты функций Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4466 Retrascope Task Closed Normal [vhdl][parser][cfg] преобразование IGSequentialWait Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5175 Retrascope Task Closed Normal [vhdl][parser] IG array elaboration Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8260 Retrascope Feature Closed Normal VHDL record support (non-aggregate case) Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
6049 Retrascope Task Closed Normal VHDL test printer: write documentation to project wiki Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
4984 Retrascope Task Closed Normal [vhdl][translator] Группировка неблокирующих присваиваний Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4925 Retrascope Task Closed Normal [vhdl][translator] Обработка непрерывных присваиваний Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9012 Retrascope Test Suite Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
10031 MicroTESK for PowerPC Bug New Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for PowerPC - 0.0 Actions
9892 MicroTESK for RISC-V Bug Closed Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for RISC-V - 0.1 Actions
2494 CTESK Bug New Normal warning at build log Sergey Smolov Alexey Demakov Actions
9376 MicroTESK for MIPS Bug New Normal Warning: Group MIPS64FpuOp contains two items add_fmt and mfc1 with the same opcode 01000100000000000000000000000000 Sergey Smolov Alexander Kamkin Actions
10082 Retrascope Bug New Normal WARNING: Illegal reflective access by org.python.core.PySystemState Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9503 Retrascope Feature Closed Normal when debug option is enabled, pass it to the model checker as well Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
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