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# Project Tracker Status Priority Subject Author Assignee Target version
3624 С++TESK Development Environment Task Closed Normal XML dumping\parsing Sergey Smolov Sergey Smolov Actions
3623 С++TESK Development Environment Task Closed Normal Внутреннее представление для прототипов тестовых систем Sergey Smolov Sergey Smolov Actions
3622 Retrascope Bug Closed Normal DFGElementaryCyclesTest & DFGClusterStatisticsTest - java.lang.OutOfMemoryError: Java heap space Sergey Smolov Sergey Smolov Actions
3590 C++TESK Testing ToolKit Bug Closed Normal C++TesK installation fails on OpenSUSE 12.2 x64 Sergey Smolov Sergey Smolov C++TESK Testing ToolKit - 1.0 Actions
3565 Local Support Project Bug Closed Normal Перестали приходить уведомления на почту об изменениях в проектах Sergey Smolov Alexey Demakov Actions
3528 Local Support Project Bug Closed Normal Не отображается полный адрес svn-репозиториев Sergey Smolov Alexey Demakov Actions
3434 Retrascope Task Closed Normal Извлечение "протоопераций" из Data Flow Graph Sergey Smolov Sergey Smolov Actions
3406 Retrascope Task Closed Normal CFG extraction from guarded atomic actions (GAA) set. Sergey Smolov Sergey Smolov Actions
2224 С++TESK Development Environment Task Closed Normal Добавить пункт со сведениями о плагине Sergey Smolov Alexander Kamkin Actions
9844 Retrascope Test Suite Bug Rejected Normal Bash scripts that run side tools (EBMC, SymbiYosys, Verilog2SMV) can't extract names of several Verilog modules Sergey Smolov Sergey Smolov Actions
9839 Retrascope Test Suite Task Rejected Normal scripts for commercial FV tools running Sergey Smolov Sergey Smolov Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9215 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_mem: Module 'AddrStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9213 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_arbiter: Module 'ArbiterStatus' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8304 Retrascope Feature Rejected Normal SLR values number limit Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7723 Retrascope Task Rejected Normal Support for module instances in Verilog descriptions Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
7594 Retrascope Bug Rejected Normal ModelSim shows error when TST file contains multiple comments Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7423 Retrascope Bug Rejected High rnd_fsm.vhd: empty tst file Sergey Smolov Igor Melnichenko Retrascope - 0.2 Actions
7081 Retrascope Task Rejected Normal xor-composition-printer Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6990 Retrascope IDE Task Rejected Normal use veditor 1.2.1c Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
6989 Retrascope IDE Task Rejected Normal migrate to Eclipse Mars (4.5) Sergey Smolov Sergey Smolov Retrascope IDE - 0.1 Actions
6808 Retrascope Task Rejected High Split CFG processes into independent parts Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
6511 Retrascope Task Rejected Normal keep expressions at case statements Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6509 Retrascope Task Rejected Normal merge embedded switch nodes with conditions depending exactly from the same variable(s) Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
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