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# Project Tracker Status Priority Subject Author Assignee Target version
5549 Retrascope Task Closed Normal [vhdl][cfg][parser] add support of instantiation Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
4466 Retrascope Task Closed Normal [vhdl][parser][cfg] преобразование IGSequentialWait Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5175 Retrascope Task Closed Normal [vhdl][parser] IG array elaboration Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
8260 Retrascope Feature Closed Normal VHDL record support (non-aggregate case) Sergey Smolov Maxim Chudnov Retrascope - 1.0 Actions
6049 Retrascope Task Closed Normal VHDL test printer: write documentation to project wiki Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
4984 Retrascope Task Closed Normal [vhdl][translator] Группировка неблокирующих присваиваний Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4925 Retrascope Task Closed Normal [vhdl][translator] Обработка непрерывных присваиваний Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9012 Retrascope Test Suite Bug Closed Normal VisBufferAllocVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Actions
9892 MicroTESK for RISC-V Bug Closed Normal WARNING: An illegal reflective access operation has occurred Sergey Smolov Alexander Protsenko MicroTESK for RISC-V - 0.1 Actions
9503 Retrascope Feature Closed Normal when debug option is enabled, pass it to the model checker as well Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
9041 Retrascope Feature Closed Normal when model checker returns an error, print it's log to the Retrascope output Sergey Smolov Mikhail Lebedev Retrascope - 1.0 Actions
6389 Retrascope Task Closed Normal Wiki documentation about testbench simulation Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5482 Retrascope Task Closed Normal [wiki] documentation for 0.1-alpha Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6976 Retrascope Task Closed Normal Wiki update Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5142 Retrascope Task Closed Normal [wiki] Классификация Engine Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9373 QEMU4V Task Closed Normal write a PowerPC-related chapter to "Getting Started" Sergey Smolov Maxim Chudnov QEMU4V - 0.3 Actions
8957 Verilog Translator Bug Closed High wrong datatype for arrays Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10041 QEMU4V Bug Closed Normal wrong names for PowerPC registers in trace Sergey Smolov Sergey Smolov QEMU4V - 0.3 Actions
3624 С++TESK Development Environment Task Closed Normal XML dumping\parsing Sergey Smolov Sergey Smolov Actions
6293 Retrascope Bug Closed Normal XmlTestParserTestCase: NoSuchMethodException Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
8283 Retrascope Bug Closed Normal "X <= (others => '0')" should be translated properly when X is bit vector Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
5465 Fortress Task Closed Normal [z3][solver] solver errors elaboration scheme Sergey Smolov Andrei Tatarnikov Fortress - 0.3 Actions
6106 MicroTESK Bug Closed Normal zero opcodes for instructions in Tarmac log Sergey Smolov Andrei Tatarnikov MicroTESK - 2.2 Actions
4358 Retrascope Bug Closed Normal Внести исправления в представление CGA и методы их извлечения Sergey Smolov Sergey Smolov Actions
3623 С++TESK Development Environment Task Closed Normal Внутреннее представление для прототипов тестовых систем Sergey Smolov Sergey Smolov Actions
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