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# Project Tracker Status Priority Subject Author Assignee Target version
3654 С++TESK Development Environment Task Closed High source code refactoring Sergey Smolov Sergey Smolov Actions
6808 Retrascope Task Rejected High Split CFG processes into independent parts Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7098 Verilog Translator Bug Closed Normal src/test/verilog/mips16/data_mem.v: 'mem_access_addr' has null declaration Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10099 Trace Matcher Feature Resolved Normal "--start-addr <hex value>" command line option Sergey Smolov Sergey Smolov Trace Matcher - 0.1 Actions
6051 Retrascope Task Closed Normal state-like variable names option Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6453 Retrascope Task Closed Normal Statement class for grouping CFG nodes Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5683 Retrascope Task Closed Normal STD_LOGIC/STD_ULOGIC processing Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5481 Retrascope Task Closed Normal [structure] remove raw packages from main build folder Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
9310 Retrascope Task Closed Normal substitute SMT-LIB variables those names are equal to builtin commands Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9227 Retrascope Feature Closed High support for 'BVEXTRACT(x y (SELECT z w))' constructions in left hand sides of assigments Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9039 Retrascope Feature Closed Normal Support for designs that assign to variable more than once Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
7723 Retrascope Task Rejected Normal Support for module instances in Verilog descriptions Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
6892 Retrascope Bug Closed Normal support for non-zero starting bitvectors Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7524 Verilog Translator Task Closed Normal support for non-zero-starting bit vector variables & signals Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5569 Retrascope Task Closed Normal support process variable declarations Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
10060 Retrascope Feature Resolved High Support SVA properties in CFG model Sergey Smolov Sergey Smolov Retrascope - 1.2 Actions
6449 Retrascope Task New Low testbench generator taking test sequences and mappings as inputs Sergey Smolov Sergey Smolov Retrascope - 2.0 Actions
5145 Retrascope Task Closed Normal [testbench] Iface Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
10287 Retrascope Feature Verified Normal TestModel: keep top level module name & variables Sergey Smolov Sergey Smolov Retrascope - 1.1 Actions
9564 Retrascope Test Suite Task Closed Normal tests for EBMC tool Sergey Smolov Sergey Smolov Actions
9565 Retrascope Test Suite Task Closed Normal tests for Verilog2SMV tool Sergey Smolov Sergey Smolov Actions
9566 Retrascope Test Suite Task Closed Normal tests for Yosys-SMTBMC tool Sergey Smolov Sergey Smolov Actions
9010 Retrascope Test Suite Bug Closed Normal Texas97CacheCoherenceVerilogPrinterTestCase: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Actions
9011 Retrascope Test Suite Bug Closed Normal Texas97IFetchVerilogPrinterTestCase: java.lang.IndexOutOfBoundsException: 4294967283 is out of bounds. Sergey Smolov Sergey Smolov Actions
9172 Retrascope Test Suite Bug Closed Normal Texas97ParsepackCfgGraphMlTestCase: ru.ispras.retrascope.basis.exception.RetrascopeException: Wrong range: 0 < 0 or 7 > 1. Sergey Smolov Sergey Smolov Actions
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