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# Project Tracker Status Priority Subject Author Assignee Target version
5456 Retrascope Task Closed Normal [structure] Замечания по структуре каталогов Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9310 Retrascope Task Closed Normal substitute SMT-LIB variables those names are equal to builtin commands Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9227 Retrascope Feature Closed High support for 'BVEXTRACT(x y (SELECT z w))' constructions in left hand sides of assigments Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
9039 Retrascope Feature Closed Normal Support for designs that assign to variable more than once Sergey Smolov Sergey Smolov Retrascope - 1.0 Actions
6892 Retrascope Bug Closed Normal support for non-zero starting bitvectors Sergey Smolov Sergey Smolov Retrascope - 0.2 Actions
7524 Verilog Translator Task Closed Normal support for non-zero-starting bit vector variables & signals Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5569 Retrascope Task Closed Normal support process variable declarations Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
10202 Verilog Translator Bug Closed Normal SVA grammar warnings via assembling Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9936 Verilog Translator Bug Closed High tabs in "`define" directive cause java.lang.NumberFormatException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9288 QEMU4V Bug Closed Immediate /target/mips/translate.c:2617:9: error: ‘else’ without a previous ‘if’ Sergey Smolov Maxim Chudnov QEMU4V - 0.2 Actions
7730 MicroTESK Bug Closed High [tarmac-logger] missing "<cpu>" tag Sergey Smolov Andrei Tatarnikov MicroTESK - 2.4 Actions
8848 Verilog Translator Bug Closed Normal test_07_08_00_1.v: Module 'pullup' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8847 Verilog Translator Bug Closed Normal test_17_01_01_2_1.v: Module 'pulldown' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8846 Verilog Translator Bug Closed Normal test_19_04_00_3.v: Module 'real_last' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5145 Retrascope Task Closed Normal [testbench] Iface Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
5443 Retrascope Bug Closed Normal [test][engine][media] TestVhdlTestbenchPrinterTestCase -> java.lang.RuntimeException: The exception has occurred while printing test pattern file Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5709 Retrascope Bug Closed Normal TestMinimiser.java:43: warning - @param argument "test" is not a parameter name. Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
9564 Retrascope Test Suite Task Closed Normal tests for EBMC tool Sergey Smolov Sergey Smolov Actions
9565 Retrascope Test Suite Task Closed Normal tests for Verilog2SMV tool Sergey Smolov Sergey Smolov Actions
9566 Retrascope Test Suite Task Closed Normal tests for Yosys-SMTBMC tool Sergey Smolov Sergey Smolov Actions
5827 Retrascope Bug Closed Normal TestVhdlTestbenchPrinterDummyTestCase -> NoSuchFileException Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5828 Retrascope Bug Closed Normal TestVhdlTestbenchPrinterVhdlTestCase -> IllegalArgumentException: Unexpected event value: true Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
6280 Retrascope Bug Closed Normal TestVhdlTestbenchPrinterVhdlTestCase: The exception has occurred while printing test pattern file Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
5433 Fortress Task Closed Normal [test] write executable SMT-LIB code at testcase comments Sergey Smolov Artem Kotsynyak Fortress - 0.3 Actions
6279 Retrascope Bug Closed Normal TestXmlPrinterTestCase: IllegalArgumentException: Output file name isn't specified Sergey Smolov Igor Melnichenko Retrascope - 0.1 Actions
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