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# Project Tracker Status Priority Subject Author Assignee Target version
9224 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PCI_BUS_Verilog_MV_files_PCInorm: ERROR: Function declaration '$random' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9594 Verilog Translator Bug Closed Normal extra 'BVEXTRACT' operation in right hand side expression in 'assign' block's statement Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9214 Verilog Translator Bug Rejected High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PPC60X_bus_src_cpu: Module 'AddressTenure' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9211 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.verilog.parser.model.VerilogModule.addDeclaration(VerilogModule.java:193) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9212 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Vlunc_vlunc: Module 'transform' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9798 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Bug9798TestCase: incorrect BVEXTRACT params for bit vector variable with offset Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8854 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_02_2: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9822 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Starting points limit has been exhausted: 513 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8858 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_01_2: java.lang.IllegalStateException: Parameter is not a value: (BVZEROEXT 2147483646 i) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8849 Verilog Translator Bug Verified Normal VerilogIeeeTestCase.runTest_04_10_01_1 [floating point parameters]: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9902 Verilog Translator Bug New High java.lang.IllegalArgumentException: Descriptor for 'dma_chsel.arb_chcsr_reg' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9775 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8831 Verilog Translator Bug Closed Normal vcegar-benchmarks/ipbdp/ipbdp_hier.v: java.lang.IllegalArgumentException: Bit vector sizes do not match: 4 != 32. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9803 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.MulFifoTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator$1.getNode(VerilogElaborator.java:932) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug New Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9296 Verilog Translator Bug Closed High vcegar-tests/cache_coherence/two_processor_bin_2.v:46: illegal types of "then" and "else" expressions : unsigned word[1] and boolean Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9210 Verilog Translator Bug Closed High java.lang.IllegalArgumentException at ru.ispras.fortress.expression.Nodes.bvextract(Nodes.java:322) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9173 Verilog Translator Bug Closed High Incorrect DataType: BIT_VECTOR(1) instead of BIT_VECTOR(40) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8850 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_1: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9182 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.MulFifoTestCase: java.lang.IllegalStateException: Parameter is not a value: i Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9190 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.DescriptorBuffersTestCase: incorrect calculation for string parameter values Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8832 Verilog Translator Bug Closed Normal verilog/opencores/mips16/IF_stage.v: java.lang.IllegalStateException: Parameter is not a value: (BVSUB 8 1) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9160 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: Module 'mips_16_core_top' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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