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# Project Tracker Status Priority Subject Author Assignee Target version
4991 Retrascope IDE Bug Closed Normal Не передается путь к HDL-описанию Sergey Smolov Alexander Kamkin Actions
10094 MicroTESK Bug Verified Normal strange common code at LinkerScript.stg Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
10513 Verilog Translator Bug New Normal macOS related line endings at Verilog modules Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10502 Verilog Translator Bug New Normal subbytes.v line 76:13 no viable alternative at input '[' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5385 Java SoftFloat Bug Closed Normal Странная структура директорий проекта Sergey Smolov Alexander Kamkin Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10215 Verilog Translator Bug New Normal ERROR: Starting points limit has been exhausted: 2255 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10510 Verilog Translator Bug New Normal ERROR: [Internal] Bit vector sizes do not match: 32 != 2. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9063 MicroTESK Bug Closed Normal microtesk/src/main/java/core/ru/ispras/microtesk/utils/PropertyMap.java uses unchecked or unsafe operations Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
10509 Verilog Translator Bug New Normal ERROR: [Internal] 0 must be > 0 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8849 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_04_10_01_1 [floating point parameters]: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10121 MicroTESK Bug Open Normal technical output printing at 'compile.sh' script running with '--help' option Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
8681 Retrascope Bug Closed Normal EngineRegistry fails to create toolchain when HashSet\HashMap are used Sergey Smolov Alexander Kamkin Retrascope - 1.0 Actions
10512 Verilog Translator Bug New Normal ADDA162H90A_atop.v line 120:47 mismatched input ':' expecting RPAREN Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10508 Verilog Translator Bug New Normal ERROR: [Internal] Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9376 MicroTESK for MIPS Bug New Normal Warning: Group MIPS64FpuOp contains two items add_fmt and mfc1 with the same opcode 01000100000000000000000000000000 Sergey Smolov Alexander Kamkin Actions
9475 Retrascope RISC-V Benchmark Bug Closed Normal Picorv32Hx8kdemoVerilogPrinterTestCase: ERROR: line 1:0 no viable alternative at input '(' Sergey Smolov Alexander Kamkin Actions
9377 MicroTESK for MIPS Bug New Normal 'Failed to construct decoder' warnings in project's build log Sergey Smolov Alexander Kamkin Actions
5404 Retrascope Bug Closed Normal [verilog][parser][cfg] java.lang.IllegalArgumentException: Unsupported data type: UNKNOWN Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
9436 MicroTESK Bug Closed Normal ru.ispras.microtesk.mmu.translator.GeneralTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin MicroTESK - 2.5 Actions
5096 Retrascope Bug Closed Normal [basis] FileCreator: "Can't create file" error Sergey Smolov Alexander Kamkin Retrascope - 0.1 Actions
10505 Verilog Translator Bug New Normal ERROR: [Internal] 11 must be within range [0, 1) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9594 Verilog Translator Bug Closed Normal extra 'BVEXTRACT' operation in right hand side expression in 'assign' block's statement Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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