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# Project Tracker Status Priority Subject Author Assignee Target version
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9848 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.VerilogVisVerilog2SmvTestCase.runTest_Pci_Bus_Verilog_Mv_files_PciNorm: Function declaration '$ND' has not been found Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10214 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000: nut_000_lut.v line 7:0 no viable alternative at input 'module' Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7098 Verilog Translator Bug Closed Normal src/test/verilog/mips16/data_mem.v: 'mem_access_addr' has null declaration Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9784 Verilog Translator Bug Closed Normal mul_fifo.v: wrong Fortress-based node representation of assignment left-hand side Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7474 Verilog Translator Bug Closed Normal missing empty branches for 'if' statements Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8786 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.FifoTestbenchTestCase fails Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9207 Verilog Translator Task Closed Normal add VCEGAR benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9208 Verilog Translator Task Closed Normal add Verilog2Smv\VIS benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9206 Verilog Translator Task Closed Normal add Texas97 benchmark to project test suite Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9311 Verilog Translator Task Closed High type casting of expression operands Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
7524 Verilog Translator Task Closed Normal support for non-zero-starting bit vector variables & signals Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
10009 Verilog Translator Task Closed Normal README\ChangeLog -> README.md\ChangeLog.md Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8205 Verilog Translator Task Closed Normal Gradle-based build environment Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5881 Verilog Translator Task Closed Normal keep file names in the AST top nodes Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5651 Verilog Translator Task Closed Normal Translate logic operation results into Boolean expressions Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9771 Verilog Translator Task Closed Normal fix 'publishing' block behaviour for Gradle 4.10.3 Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
5873 Retrascope Bug Closed High missing transitions in b04 EFSM Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6413 Retrascope Bug Closed Normal b03.vhd: different EFSM extraction stats Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
3605 Retrascope Bug Rejected Normal [vhdl][parser][cfg] Zamia не обрабатывает пакеты функций Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
6443 Retrascope Bug Closed Normal print error message when "--toplevel" value is wrong Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4926 Retrascope Bug Closed Normal [cfg][model] Путаница с наследниками CfgNode Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4836 Retrascope Bug Closed Normal [cfg][transformer][cgaa] java heap space error at control.vhd\mlite2sram.vhd Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4928 Retrascope Bug Rejected Normal [cfg] Range может состоять из нескольких участков Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
4357 Retrascope Bug Closed Normal [cfg][transformer][cgaa] Внести исправления в методы извлечения clock-like variables Sergey Smolov Sergey Smolov Retrascope - 0.1 Actions
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