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# Project Tracker Status Priority Subject Author Assignee Target version
9962 Verilog Translator Bug Verified High ru.ispras.verilog.parser.sample.Mips16CoreTopTestCase: java.lang.IllegalArgumentException Sergey Smolov Alexey Danilov Verilog Translator - 0.1 Actions
9232 Verilog Translator Task Closed High remove typedefs from texas97-tests/PPC60X_bus/src/define.v Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9226 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_small_pipeline_pipeline_smv: /src/test/verilog/vcegar-tests/small/pipeline/pipeline_smv.v line 38:10 no viable alternative at input 'property' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9225 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_MPEG_prefixcode: ERROR: ../texas97-tests/MPEG/prefixcode.v line 70:8 no viable alternative at input ';' Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9223 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogVcegarTestCase.runTest_pj_icu_icctl1: ERROR: Declaration of 'clk' has not been found Sergey Smolov Mikhail Lebedev Verilog Translator - 0.1 Actions
9230 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_multi_master_bus: java.lang.IllegalArgumentException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9231 Verilog Translator Bug Closed High ru.ispras.verilog.parser.VerilogTexas97TestCase.runTest_PI_BUS_single_master_master2: java.lang.NullPointerException Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
8786 Verilog Translator Bug Closed High ru.ispras.verilog.parser.sample.FifoTestbenchTestCase fails Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9311 Verilog Translator Task Closed High type casting of expression operands Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9209 Verilog Translator Bug Closed High java.util.EmptyStackException at ru.ispras.verilog.parser.util.TokenSourceStack.getLastParentToken(TokenSourceStack.java:70) Sergey Smolov Sergey Smolov Verilog Translator - 0.1 Actions
9775 Verilog Translator Bug Verified Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_04_1: Conversion = ''' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9594 Verilog Translator Bug Closed Normal extra 'BVEXTRACT' operation in right hand side expression in 'assign' block's statement Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9276 Verilog Translator Bug Rejected Normal no errors returned for bug-with-macro-containing module Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8856 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_10_04_05_1: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8855 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_10_03_00_5: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8831 Verilog Translator Bug Closed Normal vcegar-benchmarks/ipbdp/ipbdp_hier.v: java.lang.IllegalArgumentException: Bit vector sizes do not match: 4 != 32. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10131 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogIwlsTestCase.runTest_iscas_s9234_1: java.lang.OutOfMemoryError: Java heap space Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8850 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_1: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8865 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_19_11_00_1: java.lang.IllegalArgumentException: Declaration=DECLARATION(), parent=MODULE(m2) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8851 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_3: java.lang.IllegalArgumentException: 0 must be > 0 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8857 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_02_02_2_1: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8863 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_17_02_04_4_1: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8862 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_08_02_1: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8848 Verilog Translator Bug Closed Normal test_07_08_00_1.v: Module 'pullup' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10215 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_000_lut: ERROR: Starting points limit has been exhausted: 2255 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10241 Verilog Translator Bug New Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_dctub_jpeg: ERROR: ..\src\test\verilog\hdl-benchmarks\hdl\quip\oc_video_compression_systems_jpeg\dct_cos_table.v line 1:70 mismatched character '\r' expecting '\n' Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9773 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogIeeeTestCase.runTest_10_04_03_1: ru.ispras.fortress.expression.NodeOperation cannot be cast to ru.ispras.fortress.expression.NodeValue Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8852 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_01_14_4: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
7725 Verilog Translator Task Closed Normal bitvector arrays support Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
5492 Verilog Translator Bug Closed Normal retrascope + sapic.v = java.lang.IllegalStateException: Operand is not a constant integer value: 00000000000000000000000000000011 Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9802 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.FuncTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator.createVariableAndBinding(VerilogElaborator.java:512) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8860 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_02_4: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9790 Verilog Translator Task New Normal external names for unnamed generate blocks Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
10246 Verilog Translator Bug Rejected Normal ru.ispras.verilog.parser.VerilogQuipTestSuite#runTest_nut_001: ERROR: Module 'lut_output' has not been found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9803 Verilog Translator Bug Closed Normal ru.ispras.verilog.parser.sample.MulFifoTestCase: NullPointerException at ru.ispras.verilog.parser.elaborator.VerilogElaborator$1.getNode(VerilogElaborator.java:932) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8982 Verilog Translator Task New Normal "for" loop unrolling Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8849 Verilog Translator Bug Verified Normal VerilogIeeeTestCase.runTest_04_10_01_1 [floating point parameters]: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8861 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_03_1: java.lang.IllegalStateException: BigInteger data is not convertible to Boolean. Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8858 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_01_2: java.lang.IllegalStateException: Parameter is not a value: (BVZEROEXT 2147483646 i) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9859 Verilog Translator Task New Normal modify "ERROR: [Internal] null" line at error log Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8864 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_17_10_02_1_i: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8853 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_01_2: java.lang.IllegalArgumentException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8854 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_05_02_02_2: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
9904 Verilog Translator Task Verified Normal add info for "--library-file" cmdline option Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8859 Verilog Translator Bug Closed Normal VerilogIeeeTestCase.runTest_12_04_02_3: java.lang.NullPointerException Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8832 Verilog Translator Bug Closed Normal verilog/opencores/mips16/IF_stage.v: java.lang.IllegalStateException: Parameter is not a value: (BVSUB 8 1) Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8846 Verilog Translator Bug Closed Normal test_19_04_00_3.v: Module 'real_last' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8847 Verilog Translator Bug Closed Normal test_17_01_01_2_1.v: Module 'pulldown' cannot be found Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8779 Verilog Translator Bug Closed Normal mips16/data_mem.v: wrong type for define-containing declaration of 'ram_addr' wire Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
8738 Verilog Translator Bug Closed Normal DataMemTestCase falls with error Sergey Smolov Alexander Kamkin Verilog Translator - 0.1 Actions
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